HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 146

IC H8/SLP MCU FLASH 80QFP

HD64F38024DV

Manufacturer Part Number
HD64F38024DV
Description
IC H8/SLP MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300L SLPr
Datasheets

Specifications of HD64F38024DV

Core Processor
H8/300L
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI
Peripherals
LCD, PWM, WDT
Number Of I /o
51
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F38024DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 5 Power-Down Modes
5.1.1
The operation mode is selected using the system control registers described in table 5.3.
Table 5.3
Name
System control register 1
System control register 2
System Control Register 1 (SYSCR1)
SYSCR1 is an 8-bit read/write register for control of the power-down modes.
Upon reset, SYSCR1 is initialized to H'07.
Bit 7—Software Standby (SSBY)
This bit designates transition to standby mode or watch mode.
Bit 7
SSBY
0
1
Rev. 8.00 Mar. 09, 2010 Page 124 of 658
REJ09B0042-0800
Bit
Initial value
Read/Write
11. On the H8/38124 Group, operates only when the on-chip oscillator is selected; otherwise stops and stands by. On
the H8/38024, H8/38024S, and H8/38024R Group, stops and stands by.
System Control Registers
System Control Registers
Description
When a SLEEP instruction is executed in active mode,
a transition is made to sleep mode
When a SLEEP instruction is executed in subactive mode, a transition is made to
subsleep mode
When a SLEEP instruction is executed in active mode, a transition is made to
standby mode or watch mode
When a SLEEP instruction is executed in subactive mode, a transition is made to
watch mode
SSBY
R/W
7
0
STS2
R/W
6
0
STS1
R/W
Abbreviation
SYSCR1
SYSCR2
5
0
STS0
R/W
4
0
LSON
R/W
R/W
R/W
R/W
3
0
H'07
H'F0
Initial Value
2
1
MA1
R/W
1
1
(initial value)
Address
H'FFF0
H'FFF1
MA0
R/W
0
1

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