HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 344

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 Timers
Bit 6
OVL
0
1
Bit 5—Reserved
Bit 5 is a readable/writable reserved bit. It is initialized to 0 by a reset.
Bit 4—Channel Select (CH2)
Bit 4 selects whether ECH and ECL are used as a single-channel 16-bit event counter or as two
independent 8-bit event counter channels. When CH2 is cleared to 0, ECH and ECL function as a
16-bit event counter which is incremented each time an event clock is input to the AEVL pin. In
this case, the overflow signal from ECL is selected as the ECH input clock. When CH2 is set to 1,
ECH and ECL function as independent 8-bit event counters which are incremented each time an
event clock is input to the AEVH or AEVL pin, respectively.
Bit 4
CH2
0
1
Bit 3—Count-up Enable H (CUEH)
Bit 3 enables event clock input to ECH. When 1 is written to this bit, event clock input is enabled
and increments the counter. When 0 is written to this bit, event clock input is disabled and the
ECH value is held. The AEVH pin or the ECL overflow signal can be selected as the event clock
source by bit CH2.
Bit 3
CUEH
0
1
Rev. 8.00 Mar. 09, 2010 Page 322 of 658
REJ09B0042-0800
Description
ECL has not overflowed
Clearing condition:
After reading OVL = 1, cleared by writing 0 to OVL
ECL has overflowed
Setting condition:
Set when ECL overflows from H'FF to H'00
Description
ECH and ECL are used together as a single-channel 16-bit event counter
ECH and ECL are used as two independent 8-bit event counter channels
Description
ECH event clock input is disabled
ECH value is held
ECH event clock input is enabled
(initial value)
(initial value)
(initial value)