HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 346

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 Timers
ECH is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or
as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ECL. The
external asynchronous event AEVH pin, φ/2, φ/4, φ/8, or the overflow signal from lower 8-bit
counter ECL can be selected as the input clock source. ECH can be cleared to H'00 by software,
and is also initialized to H'00 upon reset.
Event Counter L (ECL)
Bit
Initial Value
Read/Write
ECL is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or
as the lower 8-bit up-counter of a 16-bit event counter configured in combination with ECH. The
event clock from the external asynchronous event AEVL pin, φ/2, φ/4, or φ/8 is used as the input
clock source. ECL can be cleared to H'00 by software, and is also initialized to H'00 upon reset.
Clock Stop Register 2 (CKSTPR2)
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the asynchronous event counter is described here. For details of
the other bits, see the sections on the relevant modules.
Bit 3—Asynchronous Event Counter Module Standby Mode Control (AECKSTP)
Bit 3 controls setting and clearing of module standby mode for the asynchronous event counter.
AECKSTP
0
1
Rev. 8.00 Mar. 09, 2010 Page 324 of 658
REJ09B0042-0800
Bit
Initial value
Read/Write
Note: * Bits 6 and 5 are also reserved on products other than the H8/38124 Group.
LVDCKSTP *
Description
Asynchronous event counter is set to module standby mode
Asynchronous event counter module standby mode is cleared
R/W
ECL7
7
1
0
R
7
ECL6
⎯
⎯
6
1
0
R
6
ECL5
⎯
⎯
5
1
0
R
5
PW2CKSTP AECKSTP
R/W
ECL4
4
1
R
4
0
R/W
ECL3
3
1
0
R
3
WDCKSTP PW1CKSTP LDCKSTP
R/W
ECL2
2
1
R
2
0
R/W
ECL1
1
1
0
R
1
(initial value)
R/W
ECL0
0
1
R
0
0