HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 295

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Clock Stop Register 1 (CKSTPR1)
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to timer F is described here. For details of the other bits, see the
sections on the relevant modules.
Bit 2—Timer F Module Standby Mode Control (TFCKSTP)
Bit 2 controls setting and clearing of module standby mode for timer F.
TFCKSTP
0
1
9.4.3
TCF and OCRF are 16-bit read/write registers, but the CPU is connected to the on-chip peripheral
modules by an 8-bit data bus. When the CPU accesses these registers, it therefore uses an 8-bit
temporary register (TEMP).
When performing TCF read/write access or OCRF write access in 16-bit mode, data will not be
transferred correctly if only the upper byte or only the lower byte is accessed. Access must be
performed for all 16 bits (using two consecutive byte-size MOV instructions), and the upper byte
must be accessed before the lower byte.
In 8-bit mode, there are no restrictions on the order of access.
Write Access
Write access to the upper byte results in transfer of the upper-byte write data to TEMP. Next,
write access to the lower byte results in transfer of the data in TEMP to the upper register byte,
and direct transfer of the lower-byte write data to the lower register byte.
Bit:
Initial value:
Read/Write:
CPU Interface
Timer F is set to module standby mode
Timer F module standby mode is cleared
Description
⎯
⎯
7
1
⎯
⎯
6
1
S32CKSTP ADCKSTP TGCKSTP
R/W
5
1
R/W
4
1
Rev. 8.00 Mar. 09, 2010 Page 273 of 658
R/W
3
1
TFCKSTP TCCKSTP TACKSTP
R/W
2
1
REJ09B0042-0800
R/W
Section 9 Timers
1
1
(initial value)
R/W
0
1