HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 392

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 Serial Communication Interface
SCI3 operates as follows when receiving data.
SCI3 monitors the communication line, and when it detects a 0 start bit, performs internal
synchronization and begins reception. Reception is carried out in accordance with the relevant
data transfer format in table 10.11. The received data is first placed in RSR in LSB-to-MSB order,
and then the parity bit and stop bit(s) are received. SCI3 then carries out the following checks.
• Parity check
• Stop bit check
• Status check
If no receive error is found in the above checks, bit RDRF is set to 1, and the receive data is stored
in RDR. If bit RIE is set to 1 in SCR3, an RXI interrupt is requested. If the error checks identify
a receive error, bit OER, PER, or FER is set to 1 depending on the kind of error. Bit RDRF retains
its state prior to receiving the data. If bit RIE is set to 1 in SCR3, an ERI interrupt is requested.
Table 10.12 shows the conditions for detecting a receive error, and receive data processing.
Note: No further receive operations are possible while a receive error flag is set. Bits OER,
Table 10.12 Receive Error Detection Conditions and Receive Data Processing
Receive Error Abbr.
Overrun error
Framing error
Parity error
Rev. 8.00 Mar. 09, 2010 Page 370 of 658
REJ09B0042-0800
SCI3 checks that the number of 1 bits in the receive data conforms to the parity (odd or even)
set in bit PM in the serial mode register (SMR).
SCI3 checks that the stop bit is 1. If two stop bits are used, only the first is checked.
SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred from
RSR to RDR.
FER, PER, and RDRF must therefore be cleared to 0 before resuming reception.
OER
FER
PER
Detection Conditions
When the next date receive
operation is completed while bit
RDRF is still set to 1 in SSR
When the stop bit is 0
When the parity (odd or even) set
in SMR is different from that of
the received data
Receive Data Processing
Receive data is not transferred
from RSR to RDR
Receive data is transferred
from RSR to RDR
Receive data is transferred
from RSR to RDR