HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 155

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.3.5
1. When external input signal changes before/after standby mode or watch mode
2. When external input signals cannot be captured because internal clock stops
3. Recommended timing of external input signals
When an external input signal such as IRQ, WKP, or IRQAEC is input, both the high- and
low-level widths of the signal must be at least two cycles of system clock φ or subclock φ
(referred to together in this section as the internal clock). As the internal clock stops in
standby mode and watch mode, the width of external input signals requires careful attention
when a transition is made via these operating modes. Ensure that external input signals
conform to the conditions stated in 3, Recommended timing of external input signals, below
The case of falling edge capture is illustrated in figure 5.3.
As shown in the case marked "Capture not possible," when an external input signal falls
immediately after a transition to active (high-speed or medium-speed) mode or subactive
mode, after oscillation is started by an interrupt via a different signal, the external input signal
cannot be captured if the high-level width at that point is less than 2 t
To ensure dependable capture of an external input signal, high- and low-level signal widths of
at least 2 t
mode, as shown in “Capture possible: case 1” in figure 5.3.
External input signal capture is also possible with the timing shown in “Capture possible: case
2” and “Capture possible: case 3” in figure 5.3, in which a 2 t
secured.
Notes on External Input Signal Changes before/after Standby Mode
cyc
or 2 t
subcyc
are necessary before a transition is made to standby mode or watch
Rev. 8.00 Mar. 09, 2010 Page 133 of 658
cyc
Section 5 Power-Down Modes
or 2 t
cyc
subcyc
or 2 t
level width is
REJ09B0042-0800
subcyc
.
SUB