HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 460

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only)
14.2.3
LVDCNT is a read-only 8-bit up-counter. Counting begins when 1 is written to LVDE. The
counter increments using φ/4 as the clock source until it overflows by switching from H'FF to
H'00, at which time the OVF bit in the LVDSR register is set to 1, indicating that the on-chip
reference voltage generator has stabilized. If the LVD function is used, it is necessary to stand by
until the counter has overflowed. The initial value of LVDCNT is H'00.
14.2.4
CKSTPR2 is an 8-bit read/write register. It is used to control the module’s module standby mode.
Only the bits relevant to the LVD function are described in this section. Refer to the sections on
the other modules for information about the other bits.
Bit 7—LVD Module Standby Control (LVDCKSTP)
This bit is used to control setting of the LVD function to module standby status and cancellation of
that status.
Bit 7
LVDCKSTP
0
1
Note: This bit is implemented on the H8/38124 Group only. On other products it is always read as
Rev. 8.00 Mar. 09, 2010 Page 438 of 658
REJ09B0042-0800
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
1 and cannot be written to.
Low-Voltage Detection Counter (LVDCNT)
Clock Stop Register 2 (CKSTPR2)
LVDCKSTP
Description
Sets LVD to module standby status
Cancels LVD module standby status
CNT7
R/W
R
7
0
7
1
CNT6
—
—
R
6
0
6
1
CNT5
—
—
R
5
0
5
1
PW2CKSTP AECKSTP
CNT4
R/W
R
4
0
4
1
CNT3
R/W
R
3
0
3
1
WDCKSTP PW1CKSTP LDCKSTP
CNT2
R/W
R
2
0
2
1
CNT1
R/W
R
1
0
1
1
(initial value)
CNT0
R/W
R
0
0
0
1