HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 395

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Data Transfer Operations
• SCI3 initialization
Data transfer on SCI3 first of all requires that SCI3 be initialized as described in section 10.3.2,
SCI3 initialization, and shown in figure 10.5.
• Transmitting
Figure 10.11 shows an example of a flowchart for data transmission. This procedure should be
followed for data transmission after initializing SCI3.
Figure 10.11 Example of Data Transmission Flowchart (Synchronous Mode)
Sets bit SPC32 to
Clear bit TE to 0
Read bit TDRE
Read bit TEND
Write transmit
Continue data
transmission?
data to TDR
TDRE = 1?
TEND = 1?
1 in SPCR
in SCR3
in SSR
in SSR
Start
End
Yes
No
Yes
[2]
[1]
No
Yes
No
[1]
[2]
Read the serial status register (SSR) and
check that bit TDRE is set to 1, then write
transmit data to the transmit data register
(TDR). When data is written to TDR, bit
TDRE is cleared to 0 automatically, the
clock is output, and data transmission is
started. When clock output is selected,
the clock is output and data transmission
started when data is written to TDR.
When continuing data transmission, be
sure to read TDRE = 1 to confirm that
a write can be performed before writing
data to TDR. When data is written to
TDR, bit TDRE is cleared to 0 automatically.
Section 10 Serial Communication Interface
Rev. 8.00 Mar. 09, 2010 Page 373 of 658
REJ09B0042-0800