HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 123

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

executed immediately after the port mode register (or AEGSR) access without executing an
intervening instruction, the flag will not be cleared.
An alternative method is to avoid the setting of interrupt request flags when pin functions are
switched by keeping the pins at the high level so that the conditions in table 3.5 do not occur.
However, the procedure in Figure 3.7 is recommended because IECPWM is an internal signal and
determining its value is complicated.
3.4.3
Use the recommended method, given below when clearing the flags of interrupt request registers
(IRR1, IRR2, IWPR).
• Recommended method
Use a single instruction to clear flags. The bit control instruction and byte-size data transfer
instruction can be used. Two examples of program code for clearing IRRI1 (bit 1 of IRR1) are
given below.
BCLR
MOV.B R1L, @IRR1:8 (set the value of R1L to B'11111101)
Set port mode register (or AEGSR) bit
Figure 3.7 Port Mode Register (or AEGSR) Setting and Interrupt Request Flag
Clear interrupt request flag to 0
Method for Clearing Interrupt Request Flags
Execute NOP instruction
#1,
CCR I bit
CCR I bit
@IRR1:8
←
←
1
0
Clearing Procedure
Interrupts masked. (Another possibility
is to disable the relevant interrupt in
interrupt enable register 1.)
After setting the port mode register
(or AEGSR) bit, first execute at least
one instruction (e.g., NOP), then clear
the interrupt request flag to 0
Interrupt mask cleared
Rev. 8.00 Mar. 09, 2010 Page 101 of 658
Section 3 Exception Handling
REJ09B0042-0800