HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 538

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 16 Electrical Characteristics
Notes: 1. Determined by the SA1 and SA0 bits in the system control register 2 (SYSCR2).
Table 16.24
V
Rev. 8.00 Mar. 09, 2010 Page 516 of 658
REJ09B0042-0800
Item
Input pin high
width
Input pin low
width
UD pin minimum
transition width
Item
Input clock
cycle
Input clock pulse width
Transmit data delay time
(clocked synchronous)
Receive data setup time
(clocked synchronous)
Receive data hold time
(clocked synchronous)
CC
= 2.7 V to 5.5 V, AV
2. These characteristics are given as ranges between minimum and maximum values in
Asynchronous
Clocked synchronous
order to account for factors such as temperature, power supply voltage, and variation
among production lots. When designing systems, make sure to give due consideration
to the SPEC range. Please contact a Renesas sales or support representative for
actual performance data on the product.
Serial Interface (SCI3) Timing
Symbol
t
t
t
t
IH
IL
UDH
UDL
CC
Applicable
Pins
IRQ0, IRQ1,
IRQ3, IRQ4,
IRQAEC,
WKP0 to
WKP7, TMIC,
TMIF, TMIG,
ADTRG
AEVL, AEVH 0.5
IRQ0, IRQ1,
IRQ3, IRQ4,
IRQAEC,
WKP0 to
WKP7, TMIC,
TMIF, TMIG,
ADTRG
AEVL, AEVH 0.5
UD
= 2.7 V to 5.5 V, V
Symbol
t
t
t
t
t
scyc
SCKW
TXD
RXS
RXH
Min
2
2
4
Min
4
6
0.4
—
150.0 —
150.0 —
Typ
—
—
—
—
—
SS
Values
Values
Typ Max Unit
—
—
—
—
= AV
—
—
0.6
1
—
—
SS
Max
—
—
—
—
—
= 0.0 V, unless otherwise specified
t
t
t
t
t
ns
ns
cyc
subcyc
scyc
cyc
subcyc
or
or
Unit
t
t
t
t
t
t
t
t
cyc
subcyc
OSC
cyc
subcyc
OSC
cyc
subcyc
Test Condition
Test
Condition
Reference
Figure
Figure 16.5
Figure 16.5
Figure 16.6
Figure 16.6
Figure 16.6
Reference
Figure
Figure 16.4
Figure 16.4
Figure 16.7