HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 132

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 4 Clock Pulse Generators
External Clock Input Method
Connect an external clock signal to pin OSC
typical connection.
Frequency
Duty cycle
On-Chip Oscillator Selection Method (H8/38124 Group Only)
The on-chip oscillator is selected by setting the IRQAEC pin input level during resets.* Table 4.3
lists the methods for selecting the system clock oscillator and the on-chip oscillator. The IRQAEC
pin input level set during resets must be fixed at V
selected. It is not necessary to connect an oscillator to pins OSC1 and OSC2 if the on-chip
oscillator is selected. In this case, pin OSC1 should be fixed at V
Note: The system clock oscillator must be selected in order to program or erase flash memory as
Table 4.3
IRQAEC pin input level (during resets)
System clock oscillator
On-chip oscillator
Rev. 8.00 Mar. 09, 2010 Page 110 of 658
REJ09B0042-0800
* Other than watchdog timer or low-voltage detect circuit reset.
part of operations such as on-board programming. Also, when using the on-chip emulator,
an oscillator should be connected, or an external clock input, even if the on-chip oscillator
is selected.
System Clock Oscillator and On-Chip Oscillator Selection Methods
OSC
OSC
Figure 4.7 External Clock Input (Example)
1
2
Oscillator Clock (φ
45% to 55%
Open
1
, and leave pin OSC
CC
or GND, based on the oscillator to be
OSC
)
External clock input
0
Enabled
Disabled
CC
2
open. Figure 4.7 shows a
or GND.
1
Disabled
Enabled