HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 386

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 Serial Communication Interface
Clock
Either an internal clock generated by the baud rate generator or an external clock input at the
SCK
bit COM in SMR and bits SCE1 and CKE0 in SCR3. See table 10.9 for details on clock source
selection.
When an external clock is input at the SCK
rate.
When SCI3 operates on an internal clock, the clock can be output at the SCK
the frequency of the output clock is the same as the bit rate, and the phase is such that the clock
rises at the center of each bit of transmit/receive data, as shown in figure 10.4.
Data Transfer Operations
• SCI3 initialization
Before data is transferred on SCI3, bits TE and RE in SCR3 must first be cleared to 0, and then
SCI3 must be initialized as follows.
Note: If the operation mode or data transfer format is changed, bits TE and RE must first be
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REJ09B0042-0800
Clock
Serial
data
32
pin can be selected as the SCI3 transmit/receive clock. The selection is made by means of
cleared to 0.
When bit TE is cleared to 0, bit TDRE is set to 1.
Note that the RDRF, PER, FER, and OER flags and the contents of RDR are retained
when RE is cleared to 0.
When an external clock is used in asynchronous mode, the clock should not be stopped
during operation, including initialization. When an external clock is used in synchronous
mode, the clock should not be supplied during operation, including initialization.
Figure 10.4 Phase Relationship between Output Clock and Transfer Data
0
(Asynchronous Mode) (8-bit data, parity, 2 stop bits)
D0
D1
D2
D3
1 character (1 frame)
32
D4
pin, the clock frequency should be 16 times the bit
D5
D6
D7
0/1
1
32
pin. In this case
1