HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 388

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 Serial Communication Interface
• Transmitting
Figure 10.6 shows an example of a flowchart for data transmission. This procedure should be
followed for data transmission after initializing SCI3.
Rev. 8.00 Mar. 09, 2010 Page 366 of 658
REJ09B0042-0800
Figure 10.6 Example of Data Transmission Flowchart (Asynchronous Mode)
Clear bit TE to 0
Sets bit SPC32 to
Read bit TDRE
Read bit TEND
Write transmit
Continue data
transmission?
Break output?
Set PDR = 0,
data to TDR
TDRE = 1?
TEND = 1?
1 in SPCR
PCR = 1
in SCR3
in SSR
in SSR
Start
End
Yes
No
Yes
Yes
[2]
[3]
[1]
No
Yes
No
No
[1]
[2]
[3]
Read the serial status register (SSR)
and check that bit TDRE is set to 1,
then write transmit data to the transmit
data register (TDR). When data is
written to TDR, bit TDRE is cleared to 0
automatically.
(After the TE bit is set to 1, one frame of
1s is output, then transmission is possible.)
When continuing data transmission,
be sure to read TDRE = 1 to confirm that
a write can be performed before writing
data to TDR. When data is written to
TDR, bit TDRE is cleared to 0
automatically.
If a break is to be output when data
transmission ends, set the port PCR to 1
and clear the port PDR to 0, then clear bit
TE in SCR3 to 0.