HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 160

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 5 Power-Down Modes
5.7
5.7.1
If the MSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition
to active (medium-speed) mode results from IRQ
mode, timer A, timer F, timer G, IRQ
interrupt in sleep mode. A transition to active (medium-speed) mode does not take place if the I
bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register.
Furthermore, it sometimes acts with half state early timing at the time of transition to active
(medium-speed) mode.
5.7.2
Active (medium-speed) mode is cleared by a SLEEP instruction.
• Clearing by SLEEP instruction
• Clearing by RES pin
5.7.3
Operation in active (medium-speed) mode is clocked at the frequency designated by the MA1 and
MA0 bits in SYSCR1.
Rev. 8.00 Mar. 09, 2010 Page 138 of 658
REJ09B0042-0800
A transition to standby mode takes place if the SLEEP instruction is executed while the SSBY
bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and the TMA3 bit in TMA
is cleared to 0. The system goes to watch mode if the SSBY bit in SYSCR1 is set to 1 and bit
TMA3 in TMA is set to 1 when a SLEEP instruction is executed.
When both SSBY and LSON are cleared to 0 in SYSCR1 and a SLEEP instruction is executed,
sleep mode is entered. Direct transfer to active (high-speed) mode or to subactive mode is also
possible. See section 5.8, Direct Transfer, below for details.
When the RES pin is driven low, a transition is made to the reset state and active (medium-
speed) mode is cleared.
Transition to Active (Medium-Speed) Mode
Clearing Active (Medium-Speed) Mode
Operating Frequency in Active (Medium-Speed) Mode
Active (Medium-Speed) Mode
0
, or WKP
7
0
to WKP
, IRQ
1
or WKP
0
interrupts in watch mode, or any
7
to WKP
0
interrupts in standby