HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 301

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.4.5
The following types of contention and operation can occur when timer F is used.
16-bit Timer Mode
In toggle output, TMOFH pin output is toggled when all 16 bits match and a compare match
signal is generated. If a TCRF write by a MOV instruction and generation of the compare match
signal occur simultaneously, TOLH data is output to the TMOFH pin as a result of the TCRF
write. TMOFL pin output is unstable in 16-bit mode, and should not be used; the TMOFL pin
should be used as a port pin.
If an OCRFL write and compare match signal generation occur simultaneously, the compare
match signal is invalid. However, if the written data and the counter value match, a compare
match signal will be generated at that point. As the compare match signal is output in
synchronization with the TCFL clock, a compare match will not result in compare match signal
generation if the clock is stopped.
Compare match flag CMFH is set when all 16 bits match and a compare match signal is generated.
Compare match flag CMFL is set if the setting conditions for the lower 8 bits are satisfied.
When TCF overflows, OVFH is set. OVFL is set if the setting conditions are satisfied when the
lower 8 bits overflow. If a TCFL write and overflow signal output occur simultaneously, the
overflow signal is not output.
8-bit Timer Mode
a. TCFH, OCRFH
In toggle output, TMOFH pin output is toggled when a compare match occurs. If a TCRF
write by a MOV instruction and generation of the compare match signal occur simultaneously,
TOLH data is output to the TMOFH pin as a result of the TCRF write.
If an OCRFH write and compare match signal generation occur simultaneously, the compare
match signal is invalid. However, if the written data and the counter value match, a compare
match signal will be generated at that point. The compare match signal is output in
synchronization with the TCFH clock.
If a TCFH write and overflow signal output occur simultaneously, the overflow signal is not
output.
Application Notes
Rev. 8.00 Mar. 09, 2010 Page 279 of 658
REJ09B0042-0800
Section 9 Timers