HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 56

IC H8/SLP MCU FLASH 80QFP

HD64F38024DV

Manufacturer Part Number
HD64F38024DV
Description
IC H8/SLP MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300L SLPr
Datasheets

Specifications of HD64F38024DV

Core Processor
H8/300L
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI
Peripherals
LCD, PWM, WDT
Number Of I /o
51
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F38024DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 2 CPU
The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is from
H'0000 to H'00FF (0 to 255). Note that with the H8/300L Series, the lower end of the address area
is also used as a vector area. See section 3.3, Interrupts, for details on the vector area.
If an odd address is specified as a branch destination or as the operand address of a MOV.W
instruction, the least significant bit is regarded as 0, causing word access to be performed at the
address preceding the specified address. See section 2.3.2, Memory Data Formats, for further
information.
2.4.2
Effective Address Calculation
Table 2.2 shows how effective addresses are calculated in each of the addressing modes.
Arithmetic and logic instructions use register direct addressing (1). The ADD.B, ADDX, SUBX,
CMP.B, AND, OR, and XOR instructions can also use immediate addressing (6).
Data transfer instructions can use all addressing modes except program-counter relative (7) and
memory indirect (8).
Bit manipulation instructions can use register direct (1), register indirect (2), or 8-bit absolute
addressing (5) to specify the operand. Register indirect (1) (BSET, BCLR, BNOT, and BTST
instructions) or 3-bit immediate addressing (6) can be used independently to specify a bit position
in the operand.
Rev. 8.00 Mar. 09, 2010 Page 34 of 658
REJ09B0042-0800

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