HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 97

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3.1
Exception handling is performed in the H8/38024 Group, H8/38024S Group, H8/38024F-ZTAT
Group, and H8/38124 Group when a reset or interrupt occurs. Table 3.1 shows the priorities of
these two types of exception handling.
Table 3.1
Priority
High
Low
3.2
3.2.1
A reset is the highest-priority exception. The internal state of the CPU and the registers of the on-
chip peripheral modules are initialized.
3.2.2
As soon as the RES pin goes low, all processing is stopped and the chip enters the reset state.
To make sure the chip is reset properly, observe the following precautions.
• At power on: Hold the RES pin low until the clock pulse generator output stabilizes.
• Resetting during operation: Hold the RES pin low for at least 10 system clock cycles.
Reset exception handling takes place as follows.
• The CPU internal state and the registers of on-chip peripheral modules are initialized, with the
• The PC is loaded from the reset exception handling vector address (H'0000 to H'0001), after
I bit of the condition code register (CCR) set to 1.
which the program starts executing from the address indicated in PC.
Overview
Reset
Overview
Reset Sequence
Exception Source
Reset
Interrupt
Exception Handling Types and Priorities
Section 3 Exception Handling
Time of Start of Exception Handling
Exception handling starts as soon as the reset state is cleared
When an interrupt is requested, exception handling starts after
execution of the present instruction or the exception handling in
progress is completed
Rev. 8.00 Mar. 09, 2010 Page 75 of 658
Section 3 Exception Handling
REJ09B0042-0800