HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 421

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit 7—Clock Select (CKS)
Bit 7 sets the A/D conversion speed.
Bit 7
CKS
0
1
Notes: 1. With the H8/38024, H8/38024S, and H8/38024F-ZTAT operation cannot be guaranteed
Bit 6—External Trigger Select (TRGE)
Bit 6 enables or disables the start of A/D conversion by external trigger input.
Bit 6
TRGE
0
1
Note: * The external trigger (ADTRG) edge is selected by bit IEG4 of IEGR. See 1. IRQ edge
Bits 5 and 4—Reserved
Bits 5 and 4 are reserved; they are always read as 1, and cannot be modified.
2. H8/38124 Group only.
select register (IEGR) in section 3.3.2, Interrupt Control Registers, for details.
if the conversion time is less than 12.4 µs. Make sure to select a setting that gives a
conversion time of 12.4 µs or more.
With the H8/38124 Group operation cannot be guaranteed if the conversion time is less
than 6.2 μs. Make sure to select a setting that gives a conversion time of 6.2 μs or
more.
62/φ (initial value)
31/φ
Conversion Period
Description
Disables start of A/D conversion by external trigger
Enables start of A/D conversion by rising or falling edge of external trigger at pin
ADTRG *
φ = 1 MHz
62 µs
31 µs
Rev. 8.00 Mar. 09, 2010 Page 399 of 658
φ = 5 MHz
12.4 µs
— *
Conversion Time
1
Section 12 A/D Converter
REJ09B0042-0800
φ = 10 MHz *
6.2 µs
— *
1
(initial value)
2