tdat04622 ETC-unknow, tdat04622 Datasheet - Page 101

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

Data Sheet
May 2001
Agere Systems Inc.
Functional Description
Data Engine (DE) Block
Receive Data Engine (continued)
Interpacket fill separating packets always contains a multiple of 4 bytes. The SDL framer is able to detect inter-
packet fill since its value is fixed. (It has 4 bytes equal to 0x0000000, i.e., a packet length of 0x0000 with a CRC-16
of 0x0000.) Since the framer knows the length of a particular packet and can detect interpacket fill, it will predict the
start of the next frame and frame on it. The SDL frame processor supports SDL and SDL CRC modes. When oper-
ating in SDL CRC mode, a 2-byte or 4-byte CRC for the packet payload is attached to the end of the packet pay-
load prior to the next packet length. When operating in SDL mode, there is no 2-byte or 4-byte CRC for the packet
payload.
The SDL frame processor supports X
tive polynomial of x
SDL packets will periodically send its 48-bit scrambler state within the data stream such that the receive side can
synchronize its scrambler. Whenever the SDL frame processor receives a scrambler state, it is immediately put
into sync state, which allows it to send data out. Upon receiving additional scrambler states, the scrambler will
compare its own state with the state received. If the scrambler states match, then the scrambler remains in sync
state. However, if there is a mismatch, the scrambler is put into postsync state. In postsync state, if an additional
scrambler state mismatch occurs, the X
The SDL frame processor detects scrambler state data since the packet length field of 0x001 and the length of
time separating scrambler state transmissions is programmable. Single-bit error correction for the SDL scrambler
state is incorporated within the TDAT042G5.
Both the SDL framer and the X
Besides the SDL scrambler state being transmitted, the SDL framer will also extract special A and B messages
used by the upstream device to send link layer 1 messages to the downstream hardware. The packet length field
used to detect A and B messages are 0x0002 and 0x0003, respectively.
In addition to scrambling the data, the SDL data stream coming into the SDL frame processor is dc balanced with
the 32-bit value 0xB6AB31E0.
Table 23 below is used to describe the packet length field.
Table 23. Packet Length Field
Pre-descrambler. The pre-descrambler block descrambles the payload using a self-synchronous descrambler
with a generator polynomial of 1 + x
head) is descrambled. For HDLC and PPP packets, the entire frame (including header and trailer) is descrambled.
Predescrambling, post-descrambling, or no descrambling may be selected through a provisionable register.
Packet Length
0x0004—
0xFFFF
0x0000
0x0001
0x0002
0x0003
Field
48
Interpacket fill
SDL scrambler state
A message
B message
Length of payload region for current
packets (in bytes)
+ x
28
+ x
(continued)
27
SDL Data Type
48
(continued)
+ x + 1. The X
scrambler must be synchronized before the SDL frame processor will send data.
43
48
. For ATM cell traffic, only the 48-byte cell payload (and not the cell over-
48
scrambling of the packet payload, which is accomplished by using a primi-
scrambler is resynchronized with the scrambler state it has received.
48
scrambler is not self-synchronizing. Thus, the side transmitting
155/622/2488 Mbits/s Data Interface
TDAT042G5 SONET/SDH
73