tdat04622 ETC-unknow, tdat04622 Datasheet - Page 109

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

Data Sheet
May 2001
Agere Systems Inc.
Functional Description
Data Engine (DE) Block
Transmit Data Engine (continued)
Figure 20 illustrates the configuration of the time-slot registers for four independent STS-3 signals. In this case,
there are three STS-1 signals that comprise each STS-3 signal. Since there are 12 time slots and only three are
actually required, the values in time slots 4—12 can be repetitively configured as shown in the figure or can be
configured as invalid, i.e., 0x0, 0x1, 0x2, and 0x3 for channels A, B, C, and D, respectively.
Performance Monitoring
This block contains several cell/packet counters for receive/transmit data traffic. Two 28-bit saturating counters
count the number of good packets/cells that are sent out and received by the enhanced UTOPIA interface. There
are 28-bit counters used to count the number of corrected ATM HCS single bit errors, HDLC invalid sequences,
and SDL corrected headers. Also, 28-bit counters are used to count the number of uncorrectable HCS errored
ATM cells (discarded cells), HDLC short packets, SDL errored headers, packets with bad CRC checks, and mis-
matched PPP headers. These counters are operated in latch and clear mode (using PMRST) to ensure GR-256
standards compliance. It is intended that these counters be polled at least once per second so that no error events
are missed.
Figure 20. Example of Tx/Rx Sequencer Configuration: 4xSTS-3c into Four Independent OC-3 Signals
0 x 4
0 x 5
0 x 6
0 x 7
12
3a
3b
3d
3c
0 x 4
0 x 5
0 x 6
0 x 7
11
2a
2b
2c
2d
0 x 4
0 x 5
0 x 6
0 x 7
1a
1b
1d
1c
10
0 x 4
0 x 5
0 x 6
0 x 7
0 x 4
0 x 5
0 x 6
0 x 7
(continued)
3a
3b
3c
3d
9
→
→
→
→
(continued)
0 x 4
0 x 5
0 x 6
0 x 7
2a
2b
2c
2d
PAYLOAD VALID TO CHANNEL 0
PAYLOAD VALID TO CHANNEL 1
PAYLOAD VALID TO CHANNEL 2
PAYLOAD VALID TO CHANNEL 3
8
0 x 4
0 x 5
0 x 6
0 x 7
1a
1b
1c
1d
7
0 x 4
0 x 5
0 x 6
0 x 7
3a
3b
3c
3d
6
0 x 4
0 x 5
0 x 6
0 x 7
2a
2b
2d
2c
5
0 x 4
0 x 5
0 x 6
0 x 7
1a
1b
1c
1d
4
0 x 4
0 x 5
0 x 6
0 x 7
3a
3b
3d
3c
3
0 x 4
0 x 5
0 x 6
0 x 7
155/622/2488 Mbits/s Data Interface
2a
2b
2c
2d
2
0 x 4
0 x 5
0 x 6
0 x 7
1a
1b
1d
1c
1
CONFIGURE SIMILARLY
TIME-SLOT NUMBER
T
T
T
T
FOR R
X
X
X
X
TDAT042G5 SONET/SDH
_TS[12—1][15:12]
_TS[12—1][11:8]
_TS[12—1][7:4]
_TS[12—1][3:0]
REGISTER
X
SEQUENCER
5-7937(F).ar2
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