tdat04622 ETC-unknow, tdat04622 Datasheet - Page 37

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

Contents
Data Sheet
May 2001
Table 100. Registers 0x097F—0x0980, 0x098C—0x098D, 0x0999—0x099A, 0x09A6—0x09A7: PT Interrupt
Table 101. Registers (0x09B3, 0x09BF, 0x09CB, 0x09D7, 0x09E3), (0x09EF, 0x09FB, 0x0A07, 0x0A14, 0x0A20),
Table 102. Register 0x0AA4: PT One-Shot Control Parameters (WO) ................................................................198
Table 103. Registers 0x0AA6—0x0AAD, 0x0AAE, 0x0AB5, 0x0AB6—0x0ABD, 0x0ABE—0x0AC5:
Table 104. Registers 0x0AC6—0x0AF7: PT Provisioning (R/W) .........................................................................205
Table 105. Registers 0x0ACC—0x0AD1: PT Signal Fail BER Algorithm Parameters (R/W) ...............................206
Table 106. Registers 0x0AD2—0x0AD7: PT Signal Degrade BER Algorithm Parameters (R/W) .......................207
Table 107. Ns, L, M, and B Values to Set the BER Indicator ...............................................................................208
Table 108. Ns, L, M, and B Values to Clear the BER Indicator ............................................................................209
Table 109. Registers 0x0AD8—0x0AF7: Transmit J1 Data Insert (R/W) .............................................................210
Table 110. Register 0x0AF8: Scratch Register (R/W) ..........................................................................................210
Table 111. Register 0x1000: DE Macrocell Version Number (RO) ......................................................................211
Table 112. Register 0x1001, 0x1002: DE Interrupts (0x1001 is RO, 0x1002 is RO and COR/W) .......................211
Table 113. Register 0x1004: Dry Escape Marker (R/W) ......................................................................................213
Table 114. Registers 0x1010—0x1015: Sequencer Provisioning Registers (R/W) ..............................................214
Table 115. Registers 0x1016—0x1021: Egress Configuration (R/W) ..................................................................215
Table 116. Registers 0x1022—0x102D: Ingress Configuration (R/W) .................................................................219
Table 117. Registers 0x102E—0x1031: Over-Fiber Mode (Packet-Over-Fiber or POF) Control (R/W) ..............223
Table 118. Registers 0x1032—0x1036: Sequencer Cell State Registers (R/W) ..................................................225
Table 119. Registers 0x1040—0x1043: Ingress Payload Type and Mode Control (R/W) ...................................225
Table 120. Receive Type and Mode Control Summary Table (Registers 0x1040—0x1043) ...............................226
Table 121. Registers 0x1080—0x1087: ATM Framer Idle Cell Match Mask (R/W) .............................................227
Table 122. Registers 0x1088—0x108F: ATM Idle Cell Registers (R/W) ..............................................................227
Table 123. Registers 0x1090—0x1097: ATM Unassigned Cell Match Mask (R/W) .............................................228
Table 124. Registers 0x1098—0x109F: ATM Unassigned Cell Registers (R/W) .................................................228
Table 125. Registers 0x10A0—0x10A3: ATM Framer State Registers (RO) .......................................................229
Table 126. Register 0x10A4: ATM X43 Frame Control (R/W) ..............................................................................229
Table 127. Register 0x10A5: ATM X31 Frame Control (R/W) ..............................................................................230
Table 128. Register 0x10A6: ATM X31 V/W Values (R/W) ..................................................................................230
Table 129. Register 0x10A7: ATM X31 X/Y Values (R/W) ...................................................................................231
Table 130. Register 0x10A8: ATM X31 Z Value (R/W) ........................................................................................231
Table 131. Register 0x10A9: Frame State Interrupt Mask (R/W) .........................................................................232
Table 132. Register 0x10AA: Scrambler State Interrupt Mask (R/W) ..................................................................232
Table 133. Register 0x10AB: ATM Receive Debug Register (R/W) .....................................................................233
Table 134. Registers 0x10B0—0x10B3: PPP Attach (R/W) .................................................................................234
Table 135. Registers 0x10E0—0x10E3: Egress Payload Type and Mode Control (R/W) ...................................234
Table 136. Transmit Type and Mode Control Summary Table (Registers 0x10E0—0x10E3) .............................235
Table 137. Registers 0x10F0—10FB: PPP Header Value Detach (R/W) ............................................................235
Table 138. Registers 0x10FC—0x10FF: PPP Header Detach Search (R/W) ......................................................236
Table 139. Registers 0x1100—0x1107: ATM/HDLC/SDL Framer—Condition Counter 1
Table 140. Registers 0x1108—0x110F: ATM/HDLC/SDL Framer—Condition Counter 2
Table 141. Registers 0x1110—0x1117: CRC Checker—Bad Packet Counter (PMRST Update) (RO) ...............240
Table 142. Registers 0x1118—0x111F: PPP Detach—Mismatched Header Counter (PMRST Update) (RO) ...241
Table 143. Registers 0x1120—0x1127: Receive Good Packet/Cell Counter (PMRST Update) (RO) .................242
Table 144. Registers 0x1128—0x112F: Transmit Good Packet/Cell Counter (PMRST Update) (RO) ................243
Agere Systems Inc.
Mask Control (R/W) ............................................................................................................................196
(0x0A2C, 0x0A38, 0x0A44, 0x0A50, 0x0A5C), (0x0A68, 0x0A74, 0x0A80, 0x0A8C, 0x0A98):
Error Counters (RO) ...........................................................................................................................198
PT Control Parameters (R/W) ............................................................................................................199
(PMRST Update) (RO) .......................................................................................................................238
(PMRST Update) (RO) .......................................................................................................................239
List of Tables
(continued)
155/622/2488 Mbits/s Data Interface
TDAT042G5 SONET/SDH
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