tdat04622 ETC-unknow, tdat04622 Datasheet - Page 206

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface
Register Descriptions
OHP Registers
Table 80. Registers 0x042E: Transmit Control Port A (R/W) (continued)
Reset default of registers = 0x0003.
178
Address
(Hex)
042E
Bit #
9
8
7
6
5
4
(continued)
TAPSBABBLEINS[A]
TTOAC_D4TO12[A]
TTOAC_D1TO3[A]
(continued)
TTOAC_F1[A]
TTOAC_S1[A]
TTOAC_E1[A]
Name
Transmit TOAC S1 Byte Control Channel A.
Control bit, when set to logic 0, causes the
default value to be inserted into the S1 byte in
the transmit frame. Setting these bits to logic 1
causes the TTOAC value to be inserted into the
S1 byte. TTOAC_S1[A] is valid for STS-48/
STM-16 mode.
Transmit TOAC D4 to D12 Byte Control
Channel A. Control bit, when set to logic 0,
causes the default value to be inserted into the
D4 to D12 bytes in the transmit frame. Setting
these bits to logic 1 causes the TTOAC value to
be inserted into the D4 to D12 bytes.
TTOAC_D4TO12[A] is valid for STS-48/
STM-16 mode.
Transmit TOAC D1 to D3 Byte Control Chan-
nel A. Control bit, when set to logic 0, causes
the default value to be inserted into the D1 to
D3 bytes in the transmit frame. Setting these
bits to logic 1 causes the TTOAC value to be
inserted into the D1 to D3 bytes.
TTOAC_D1TO3[A] is valid for STS-48/STM-16
mode.
Transmit TOAC F1 Byte Control Channel A.
Control bit, when set to logic 0, causes the
default value to be inserted into the F1 byte in
the transmit frame. Setting these bits to logic 1
causes the TTOAC value to be inserted into the
F1 byte. TTOAC_F1[A] is valid for STS-48/
STM-16 mode.
Transmit TOAC E1 Byte Control Channel A.
Control bit, when set to logic 0, causes the
default value to be inserted into the E1 byte in
the transmit frame. Setting this bit to logic 1
causes the TTOAC value to be inserted into the
E1 byte. TTOAC_E1[A] is valid for STS-48/
STM-16 mode.
Transmit APS Babble Insert Channel A. Con-
trol bit, when set to 1, causes an inconsistent
APS byte (K1[7:0], K2[7:3]) to be inserted into
the outgoing STS-M frame until this register is
reset to 0.
Function
Agere Systems Inc.
Data Sheet
May 2001
Default
Reset
0
0
0
0
0
0