tdat04622 ETC-unknow, tdat04622 Datasheet - Page 286
tdat04622
Manufacturer Part Number
tdat04622
Description
Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
Manufacturer
ETC-unknow
Datasheet
1.TDAT04622.pdf
(310 pages)
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TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface
Interface Timing Specifications
Microprocessor Interface Timing
Synchronous Mode (continued)
ADDR[15:0] The address will be available throughout the entire cycle.
DATA[15:0]
R/W (Input)
CS (Input)
DT (Output) Data transfer acknowledge on the host bus interface is initiated on T6. DT is 3-stated when CS is
ADS (Input) Address strobe is active-low for one clock cycle, T0. When used with the Power PC (Motorola
258
(66 MHz MAX)
Figure 39. Microprocessor Interface Synchronous Read Cycle (MPMODE (Pin D8) = 1)
ADDR[15:0]
DATA[15:0]
(OUTPUT)
Read data is available in T6.
The read (H) write (L) signal is always high during the read cycle.
Chip select is an active-low signal.
high.
MPC860), this is TS (transfer start).
MPCLK
ADS
R/W
CS
DT
HIGH Z
HIGH Z
t10
t11
t8
T0
(continued)
T1
(continued)
t12
T2
T3
T4
T5
t13
t15
T6
t9
t14
t16
HIGH Z
HIGH Z
Agere Systems Inc.
Data Sheet
May 2001
5-7660(F)r.6
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