tdat04622 ETC-unknow, tdat04622 Datasheet - Page 211

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

Data Sheet
May 2001
Agere Systems Inc.
Register Descriptions
OHP Registers
Table 82. Registers 0x0430, 0x0432, 0x0434: Transmit Control Port [B—D] (R/W) (continued)
Reset default of registers = 0x0003.
0430, 0432,
Address
(Hex)
0434
Bit #
4
3
2
1
0
(continued)
TAPSBABBLEINS[B—D]
TM1_REIL_INH[B—D]
TM1_ERR_INS[B—D]
TF1INS[B—D]
TS1INS[B—D]
(continued)
Name
Transmit APS Babble Insert Channel
[B—D]. Control bit, when set to 1, causes an
inconsistent APS byte (K1[7:0], K2[7:3]) to be
inserted into the outgoing STS-M frame until
this register is reset to 0.
Transmit M1 Error Insert [B—D]. Once this
register is set to 1, an error will be inserted con-
tinuously into the outgoing M1 byte until this
register is reset to 0. In STS-48/STM-16 mode,
only TM1_ERR_INS is valid.
Transmit M1 REI-L Inhibit Channel [B—D].
Active-high to inhibit automatic insertion of
REI-L (MS-REI). In STS-48/STM-16 mode, only
TM1_REIL_INH is valid.
Transmit F1 Insert Control Channel [B—D].
Control bit, when set to a logic 1, inserts the
value in TF1DINS[7:0] into the outgoing F1 byte
in the STS-M frame; otherwise, the insert value
depends on TTOAC_F1 register. TF1INS[A] is
valid in STS-48/STM-16 mode.
Transmit S1 Insert Control Channel [B—D].
Control bit, when set to a logic 1, inserts the
value in TS1DINS[7:0] into the outgoing S1 byte
in the STS-M frame; otherwise, the insert value
depends on TTOAC_S1 register. TS1INS[A] is
valid in STS-48/STM-16 mode.
Function
155/622/2488 Mbits/s Data Interface
TDAT042G5 SONET/SDH
Default
Reset
0
0
0
1
1
183