tdat04622 ETC-unknow, tdat04622 Datasheet - Page 6

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

for Version 1 and 1A of the Device
Core Registers (CR)
CR1. Clear on Read/Clear on Write Behavior
Bit 6 of line provisioning register 0x0010 sets the functionality of the COR/W registers.
Table 1. COR/W Settings of Register 0x0010, Bit 6
Workaround
This is informational only. No workaround is available for this condition.
Corrective Action
This condition will be described in revision 4 of the advance data sheet.
Line Interface (LI)
LI1. STS-48/STM-16 Mode Lacks Facility Loopback
There is no facility loopback function (line input to line output) available in STS-48/STM-16 mode. Facility loopback
is available only in STS-12/STM-4 and STS-3/STM-1 modes as described in the advance data sheet.
Workaround
This function is not a feature of TDAT042G5.
Corrective Action
No corrective action is required for this condition.
4
Bit 6
1
0
Mode
COW
COR
After COR has been set (address 0x0010, bit 6 = 1), all registers that are accessed
are cleared when read.
After COW has been set (address 0x0010, bit 6 = 0), a 1 must be written to a given bit
in a given register to clear that bit. Writing a 0 to a bit in a given register does not clear
that bit.
Bit Clear Behavior of Accessed Registers
Agere Systems Inc.
May 2001