tdat04622 ETC-unknow, tdat04622 Datasheet - Page 58

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information
Table 5
30
AM29
AN30
AA32
AP18
AA34
AL17
H33
Pin
J32
.
Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)
TxSOP/C[D]
TxSOP/C[C]
TxSOP/C[B]
TxSOP/C[A]
Symbol
TxPA[D]
TxPA[C]
TxPA[B]
TxPA[A]
(continued)
(5 V tolerant)
Type
3.3 V
3.3 V
I/O
O
I
Transmit Start of Packet/Cell. In ATM mode, the TxSOP/C[D:A]
signal marks the start of a cell on the TxDATA[D:A][15:0] bus.
When TxSOP/C[D:A] is active, the first word of the cell is present
on the TxDATA[D:A][15:0] bus.
In packet modes, the TxSOP/C[D:A] signal marks the start of a
packet on the TxDATA[D:A][15:0] bus. When TxSOP/C[D:A] is
active, the first word of the packet is present on the
TxDATA[D:A][15:0] bus.
TxSOP/C[D:A] is considered valid only when TxENB[D:A] is
asserted, and is sampled on the rising edge of TxCLK[D:A].
In U3 or U3+ (32-bit mode), only the TxSOP/C[A] pin of port A is
used to indicate a start of packet/cell for the 32-bit data input.
Transmit Cell/Packet Available. This signal indicates when the
TDAT042G5 transmit FIFO can accept data from the master
device. If the FIFO is empty or more than the provisioned space is
available in the FIFO, TxPA[D:A] is set active.
I
I
I
* ATM Forum Technical Committee, UTOPIA Level 3, STR-PHY-UL3-01.00, July
(See further description on next page.)
1999.
One-Cycle Delay Mode. This mode follows the UTOPIA Level
2 Standard. The TxPA response occurs one cycle after the
address is polled.
Two-Cycle Delay Mode. This mode follows the UTOPIA Level
3 baselined text*. The TxPA response occurs two cycles after
the address is polled.
TxPA[D:A] Assertion. The TxPA[D:A] signal behavior relies on
the UTOPIA provisionable watermarks. In packet mode,
TxPA[D:A] goes high when the amount of data in the FIFO is
less than the high watermark setting. In ATM mode, TxPA[D:A]
goes high when the FIFO has space to receive a complete ATM
cell from the master. (This requires the high threshold to be set
appropriately by the user, i.e., set so that an entire cell can be
received once TxPA[D:A] goes active.)
Name/Description
Agere Systems Inc.
Data Sheet
May 2001