tdat04622 ETC-unknow, tdat04622 Datasheet - Page 92

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface
Functional Description
Path Terminator (PT) Block
SPE Terminate (continued)
Receive Signal Label. The C2 block will extract and validate the signal label byte (C2) and store it in a software-
accessible register. The signal label is updated when a provisionable number of consecutive detections of a new
C2 value occur (CNTDC2[A—D][3:0]; see register description, page 204). All monitoring is disabled when the
pointer is in an LOP-P or an AIS-P state. Commonly used values of C2 with their signal labels are listed below in
Table 19.
Table 19. Types of Signal Labels
Any value of C2 may be provisioned. If the provisioned value is not matched by the detected value, then data is not
passed to the DE. If the provisioned value does match the detected value, then data is passed to the DE.
TDAT042G5 will detect unequipped payloads (UNEQ-P) when a provisionable number of consecutive monitored
C2 bytes match the 0x00 unequipped STS SPE state. TDAT042G5 will detect mismatched payloads (PLM-P)
when a provisionable number of consecutive monitored C2 bytes do not match the provisioned expected payload
label (RC2EXPVAL[7:0]; see register description, page 205).
Receive Path Status. The G1 block extracts the path remote error indication (REI-P) bits of G1[7:4] and accumu-
lates the REI-P errors in a 16-bit saturating counter. This counter is operated in latch and clear mode to ensure
Bellcore and ITU compliance. It is intended that this counter be polled at least once per second in order that no
error events are missed.
RDI-P. This block will also validate the path remote defect indication (RDI-P) bits and store the result in a software-
accessible register. The receive path can monitor remote defect indications in either enhanced or single bit RDI-P
modes (provisionable via software bit RDIPMON_ENH_OR1B [A—D]; see register description, page 200). The
interpretation of the G1 byte is as follows.
Table 20. 1-bit Mode
Table 21. 3-bit Mode (Enhanced RDI)
* TIM-P must be accomplished through (microprocessor) software by reading the
64
transmit RDI-P state and inserting the G1 bit.
C2 Value
G1[3:1] = 0xx
G1[3:1] = 1xx
G1[3:1] = 001
G1[3:1] = 010
G1[3:1] = 101
G1[3:1] = 110
0x00
0x01
0x13
0x16
G1 Bytes
G1 Bytes
Unequipped STS SPE
Equipped nonspecific payload
Mapping for ATM
Mapping for HDLC-PPP
No RDI-P defects
AIS-P , LOP-P
No RDI-P defects
PLM-P or LCD-P
AIS-P or LOP-P
UNEQ-P or TIM-P (TIM-P is J1 mismatch*)
Signal Label
(continued)
(continued)
Description
Description
Agere Systems Inc.
Data Sheet
May 2001