tdat04622 ETC-unknow, tdat04622 Datasheet - Page 13

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

May 2001
Agere Systems Inc.
Data Engine (DE)
DE8. Clearing DE Interrupt Register (0x1002)
DE interrupt register 0x1002 is incorrectly defined in the revision 3 of the data sheet as RO. DE interrupt register
0x1002 is correctly defined as a COR/W register. However, register 0x1002 must be used in the COR mode (regis-
ter 0x0010 bit 6 set to 1). The bits of register 0x1002 are explained in detail in Table 4.
Table 4. Register 0x1002: DE Interrupt (COR/W)
Workaround
This is informational only. No workaround is available for this condition.
Corrective Action
This behavior will be described in future revisions of the advance data sheet.
DE9. Single Packet Transmission in HDLC-CRC, SDL-CRC, and PPP Modes
When receiving in either PPP or CRC mode, a single packet may not pass through the device. This occurs when
the end of packet (which contains the CRC) never reaches the UT FIFO. The ingress channel suspends transfer to
the UT when there is no end of packet in the FIFO. These bytes are transferred to the UT when the next packet is
received. This problem will affect HDLC-CRC, SDL-CRC, and PPP modes.
Workaround
There are two possible workarounds:
I
I
Corrective Action
This condition will be addressed in future versions of the device.
15—12
Set ingress payload type and mode control registers (0x1040—0x1043) to CRC strip mode. However, in CRC-16
mode, single packets may still get stuck if CRC ends on bytes A or B.
Send a minimum 4-byte dummy packet after each packet.
11—0
Bits
(address 0x0010, bit 6)
COR or COW
Mode
RO
(continued)
To clear these SDL Rx frame state interrupt bits, read and
clear their associated interrupt source registers
(addresses 0x14E0—0x14E3).
To properly clear these bits, device must be in COR mode
(address 0x0010, bit 6 = 1).
Clear Behavior of Register 0x1002
for Version 1 and 1A of the Device
11