tdat04622 ETC-unknow, tdat04622 Datasheet - Page 57

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

Data Sheet
May 2001
Agere Systems Inc.
Pin Information
Table 5. Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)
AM28
AM27
AM26
AM25
AM16
AM15
AM14
AM17
AP29
AN28
AP28
AN27
AP27
AR27
AN26
AP26
AR26
AP17
AP16
AN16
AR15
AP15
AN15
AR14
AP14
AN14
AP13
AN13
AN29
AB35
AL28
AL27
AL26
AL15
AL14
J33
Pin
TxDATA[C][15]
TxDATA[C][14]
TxDATA[C][13]
TxDATA[C][12]
TxDATA[C][11]
TxDATA[C][10]
TxDATA[D][15]
TxDATA[D][14]
TxDATA[D][13]
TxDATA[D][12]
TxDATA[D][11]
TxDATA[D][10]
TxDATA[C][9]
TxDATA[C][8]
TxDATA[C][7]
TxDATA[C][6]
TxDATA[C][5]
TxDATA[C][4]
TxDATA[C][3]
TxDATA[C][2]
TxDATA[C][1]
TxDATA[C][0]
TxDATA[D][9]
TxDATA[D][8]
TxDATA[D][7]
TxDATA[D][6]
TxDATA[D][5]
TxDATA[D][4]
TxDATA[D][3]
TxDATA[D][2]
TxDATA[D][1]
TxDATA[D][0]
TxPRTY[D]
TxPRTY[C]
TxPRTY[B]
TxPRTY[A]
Symbol
(continued)
(5 V tolerant)
(5 V tolerant)
(5 V tolerant)
3.3 V
3.3 V
3.3 V
Type
I/O
I
I
I
Transmit Data Channel C. Used to transport data into the
UTOPIA PHY Tx block. TxDATA[C] is only valid when TxENB[C]
is asserted, and is sampled on the rising edge of TxCLK[C].
Note that TxDATA[C] is used in various UTOPIA modes. In U2
or U2+, all 16 bits are valid. In U3 or U3+ (8-bit mode), only bits
15 to 8 are valid.
In U3 or U3+ (32-bit mode), channel C port is considered dis-
abled, and must be provisioned to the idle (default) state.
Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB).
Transmit Data Channel D. Used to transport data into the UTO-
PIA PHY Tx block. TxDATA[D] is only valid when TxENB[D] is
asserted, and is sampled on the rising edge of TxCLK[D]
(TxCLK[A] for U3+, 32-bit mode). Note that TxDATA[D] is used in
various UTOPIA modes. In U2 or U2+, all 16 bits are valid. In U3
or U3+ (8-bit mode), only bits 15 to 8 are valid.
In U3 or U3+ (32-bit mode), channel D port is considered dis-
abled, and must be provisioned to the idle (default) state.
Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB).
Transmit Parity. This signal indicates the parity on the
TxDATA[D:A][15:0] bus. A parity error raises an alarm but does
not cause the cell/packet to be dropped. Odd or even parity may
be provisioned through a software register. TxPRTY[D:A] is con-
sidered valid only when TxENB[D:A] is asserted, and is sam-
pled on the rising edge of TxCLK[D:A].
In U3 or U3+ (32-bit mode), the TxPRTY[A] parity pin of port A
indicates the parity for the entire 32-bit data input.
Name/Description
155/622/2488 Mbits/s Data Interface
TDAT042G5 SONET/SDH
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