tdat04622 ETC-unknow, tdat04622 Datasheet - Page 68

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information
Table 6. Pin Descriptions—Microprocessor Interface Signals
* I
40
u
A12
B12
C12
D12
E12
A11
B11
C11
D11
A10
B10
C10
D10
E10
Pin
C7
E7
D7
D8
C8
B8
B7
A9
B9
= I
d
= 50 kΩ, where I
MPMODE
DATA[15]
DATA[14]
DATA[13]
DATA[12]
DATA[11]
DATA[10]
Symbol
PMRST
MPCLK
DATA[9]
DATA[8]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2]
DATA[1]
DATA[0]
RST
ICT
INT
CS
u
= internal pull-up resistance and I
(continued)
(5 V tolerant)
(5 V tolerant)
(5 V tolerant)
(5 V tolerant)
(5 V tolerant)
(5 V tolerant)
(5 V tolerant)
(open drain)
Type
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
I
I/O*
I/O
u
I
I
I
I
I
O
/O Data Bus. This bus is a bidirectional data bus for writing and
u
u
u
u
u
Reset (Asynchronous) (Active-Low). Reset must be held
active-low for a minimum of 100 ns. After deassertion of reset, the
device is reset and available for use after 8 µs.
3-State Control (Active-Low). ICT has an internal 100 kΩ pull-
up. This control 3-states the digital outputs. It does not control the
LVPECL outputs.
1-Second Performance Monitor (PM) Clock. PM clock can be
generated on-chip. This signal will have a 50% duty cycle.
PMRST clock may be programmed by core register 0x0013,
bit 15 (PMRST_I/O_CTRL) to be either an output or input. As an
output clock, it is derived from the transmit line clock, TxCKP/N.
This clock is divided to produce a 1 second, 50% duty cycle clock
output. As an input, PMRST is under software control and can be
activated longer or shorter than once per second. In the software
control mode with PMRST an input, the minimum pulse width of
the external PMRST signal is 10 ms.
MPU Mode Select. This signal is set high for a synchronous
microprocessor, or low for an asynchronous microprocessor.
MPU Clock. This clock can operate from 1 Hz to 66 MHz when in
synchronous mode.
Chip Select (Active-Low). This signal must be low during regis-
ter access.
Interrupt (Active-Low). This signal goes low when the device
generates an unmasked interrupt.
reading software registers. [15:0] refers to a 16-bit data bus
(15 = MSB, 0 = LSB).
d
= internal pull-down resistance.
Name/Description
Agere Systems Inc.
Data Sheet
May 2001