tdat04622 ETC-unknow, tdat04622 Datasheet - Page 50

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information
Note: 3.3 V CMOS logic inputs are 5 V tolerant. Logic inputs can be driven from standard TTL levels, and logic out-
Table 3. Pin Descriptions—Line Interface Signals
Unused LVPECL outputs should not be terminated to minimize power consumption. Unused inputs are internally
disabled whenever core registers 0x0010 and 0x0011 are properly provisioned. The unused inputs can be consid-
ered to be NC (no connect).
22
AG2
AG1
AE2
AE1
AE4
AE3
AD2
AD1
AD4
AD3
AC3
AC2
AC5
AC4
AB2
AB1
AF2
AF1
AF4
AF3
Pin
V5
V4
puts can drive standard TTL inputs. All LVPECL buffers are differential. LVPECL is compliant with low-volt-
age (3.3 V) pseudo-emitter-coupled logic interface levels. All PECL outputs, including ECLREFHI and
ECLREFLO require terminating resistors. The required termination for the PECL buffers is 50 Ω to a termi-
nating voltage of V
GND
functionality. The name preceding the / is the function in STS-48/STM-16 mode. The name after the / is the
function in STS-3/STM-1 or STS-12/STM-4 mode.
RxCLK[D]P
RxCLK[D]N
RxD[9]N/
RxD[A]N
RxD[9]P/
RxD[A]P
RxD[0]N
RxD[1]N
RxD[2]N
RxD[3]N
RxD[4]N
RxD[5]N
RxD[6]N
RxD[7]N
RxD[8]N
RxD[0]P
RxD[1]P
RxD[2]P
RxD[3]P
RxD[4]P
RxD[5]P
RxD[6]P
RxD[7]P
RxD[8]P
Symbol
RxCKP/
RxCKN/
D
). Other termination styles are not recommended. LVPECL inputs with a / in the name indicate multiple
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
(continued)
Type
DDD
– 2 V. The Thevenin equivalent is also acceptable (130 Ω to V
I/O
I
I
I
Receive Line Clock (STS-48/STM-16)/Receive Line Data Input Channel
A. In STS-48/STM-16 mode, these pins function as receive line clock. This
155.52 MHz clock comes from an external clock data recovery circuit. This
clock is used to clock in the RxD[15:0] receive line data inputs.
In STS-3/STM-1 or STS-12/STM-4 mode, these pins function as receive
data input channel A at 155.52 Mbits/s or 622.08 Mbits/s, respectively.
This buffer is internally disabled when not in STS-48/STM-16 mode and
channel A is disabled. This buffer is internally disabled through proper pro-
visioning when the input is not active.
Receive Line Data Inputs (STS-48/STM-16). In STS-48/STM-16 mode,
these pins function as receive line data inputs [0:8]. The remaining receive
line data inputs [9:15] are listed below and are multiplexed for use in the
STS-3/STM-1 or STS-12/STM-4 modes.
The 2.488 Gbits/s STS-48/STM-16 serial data stream is converted to a
155.52 Mbits/s parallel 16-bit word external to TDAT042G5 by a demulti-
plexer.
All 32 differential data input pins, RxD[15:0]P/N, are used as the parallel
data input bus in the STS-48/STM-16 mode. These pins constitute a
155.52 Mbits/s parallel 16-bit word-aligned to the RxCKP/N 155.52 MHz
receive line clock. RxD[15] is the most significant bit and is the first bit
received. RxD[0] is the least significant bit and is the last bit received.
This buffer is internally disabled through proper provisioning when the input
is not active.
Receive Line Data Input [9]/Receive Line Clock Channel D. In STS-48/
STM-16 mode, these pins function as receive line data input [9] at
155.52 Mbits/s.
In STS-3/STM-1 or STS-12/STM-4 mode, these pins function as receive
line clock channel D at either 155.52 MHz (STS-3/STM-1) or 622.08 MHz
(STS-12/STM-4).
This buffer is internally disabled when not in STS-48/STM-16 mode and
channel D is disabled. This buffer is internally disabled through proper pro-
visioning when the input is not active.
Name/Description
DDD
Agere Systems Inc.
and 82 Ω to
Data Sheet
May 2001