tdat04622 ETC-unknow, tdat04622 Datasheet - Page 65

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

Data Sheet
May 2001
Agere Systems Inc.
Pin Information
Table 5
AP21
AK33
AN21
AK34
AM9
U34
AL9
V33
Pin
.
Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)
RxENB[D]
RxENB[C]
RxENB[B]
RxENB[A]
RxPA[D]
RxPA[C]
RxPA[B]
RxPA[A]
Symbol
(continued)
(5 V tolerant)
3.3 V
3.3 V
Type
I/O
O
I
Receive Cell/Packet Available. (continued)
I
I
Receive Data Enable (Active-Low). This signal is used to indi-
cate to the UTOPIA PHY Rx block that it is selected. If
RxENB[D:A] is high, no operation is performed. If RxENB[D:A] is
low, the UTOPIA PHY Rx block sends data (not necessarily valid
data).
In U3 or U3+ (32-bit mode), only the RxENB[A] input pin of port A
is used to enable the transfer of data.
Data Transfer. A TDAT042G5 ingress channel sends data
when it has asserted RxPA[D:A] and the master device
requests data (via RxENB[D:A]). In ATM mode, if the master
device requests data using RxENB[D:A] and if the TDAT042G5
has less than the low watermark amount of data to send and
there is no end of cell in the FIFO (RxPA[D:A] is deasserted),
then the TDAT042G5 UTOPIA interface will send out data that
should be ignored by the master, i.e., it does not send data from
its internal FIFO.
MPHY Support. When the RxPA signals are used for MPHY
direct status, the corresponding RxCLK[B, C, and/or D] must be
provided. This clock will be the same as RxCLK[A].
In ATM mode, once an ATM cell transfer starts, the Tx or Rx
side must complete the transfer. If the transfer is not com-
pleted, then the cell will be corrupted. The transfer continues
until either (1) the end of cell is reached, when the end of cell
exists below the low watermark, or (2) the end of the FIFO is
reached. If the end of the FIFO is reached, no underflow is
flagged on the receive side. In ATM mode, the low watermark
should be set so that at least one entire cell is in the FIFO prior
to asserting RxPA[D:A].
In packet mode, once the data transfer begins, the RxPA[D:A]
signal will remain asserted until the FIFO is drained if there is
no EOP below the low watermark. During the time RxPA[D:A] is
asserted, valid data is being transferred.
RxPA[D:A] is updated on the rising edge of RxCLK[D:A].
In 32-bit mode, only the RxPA[A] pin of port A is used to indi-
cate the packet/cell available status.
Name/Description
155/622/2488 Mbits/s Data Interface
TDAT042G5 SONET/SDH
37