tdat04622 ETC-unknow, tdat04622 Datasheet - Page 130

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface
Interface Description
General-Purpose I/O Bus (GPIO)
GPIO[3:0] are bidirectional pins. They can be configured individually as input or output by writing to the GPIO mode
and GPIO output configuration registers (addresses 0x0013, 0x0014, 0015; see register descriptions, page 152).
The value to be output is written into the GPIO output register (address 0x000F; see register descriptions,
page 150). To use the GPIO pins as outputs, set the GPIO output configuration bits (bits 8 and 0) to 1, and set the
GPIO mode bits GPIO[3:0]_DIRECTION_ I/O (address 0x0013, bits [3:0]) to 1.
The input value is read from the GPIO input register (address 0x000A; see register description, page148). GPIO
pins can also be used to generate an interrupt upon a change in value. An interrupt can be generated on either the
input level or edge, depending on the GPIO mode register. Figure 29 shows how the GPIO functions.
If a GPIO pin is an input, the logic value on the pin can be read from a software register. The GPIO pin can also be
programmed to generate a level-sensitive interrupt or a positive edge-triggered interrupt contributing to the external
interrupt pin.
If a GPIO pin is an output, the value provisioned will appear on the device pin immediately.
102
000A
000C BLOCK INTERRUPT MASKS
000E
000F
001F
0000
0001
0002
0003
0004
0005
0008
0010
0011
0012
0013
COMPOSITE INTERRUPTS
LOOPBACK CONTROL
LINE PROVISIONING
CHANNEL CONTROL
CORE REGISTERS
DEVICE VERSION
GPIO OUTPUTS
CORE RESETS
DEVICE NAME =
TDAT042G5
GPIO INPUTS
GPIO MODE
SCRATCH
(continued)
GPIO OUTPUTS
Figure 29. GPIO Functionality
GPIO INPUTS
INTERRUPTS
GPIO MODE
3
ACTIVE
3 2 1 0
3 2 1 0
LEVEL EDGE
3 2 1 0
2
GPIO[3:0]
DIRECTION
3 2 1 0
3
3 2 1 0
2 1 0
1
Agere Systems Inc.
+
EDGE
POS.
DET.
0
Data Sheet
May 2001
5-7058(F)r.6