tdat04622 ETC-unknow, tdat04622 Datasheet - Page 127

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

Data Sheet
May 2001
Agere Systems Inc.
Functional Description
UTOPIA (UT) Interface Block
Multi-PHY Support (continued)
The ATM side sends one RxENB (TxENB) signal to channel A for the grouped channels to select a channel which
has ATM cells/packets (or room) available. An MPHY channel is selected using the following procedures.
1.The ATM layer polls the RxPA[D:A] (TxPA[D:A]) status of a channel by placing its address on the RxADDR[4:0]
2.In the following cycle, the MPHY channel gives its status by driving RxPA[D:A] (TxPA[D:A]) of channel A.
3.The ATM side selects the MPHY channel by placing the desired MPHY address on the address bus
4.During the next cycle, the ATM side asserts RxENB[D:A] (TxENB[D:A]), and the selection of an MPHY channel is
Only one MPHY channel at a time is selected for a cell/packet transfer when ATM drives RxENB (TxENB) for
channel A from high to low. However, another MPHY channel can be polled for its RxPA (TxPA) status while the
selected channel transfers data.
Figure 28 shows an example of the single-cycle RxPA response of each channel. In this figure, channels A, B, C,
and D have Rx addresses 00, 01, 02, and 03, respectively. RxPA[A] shows the packet availability of all four chan-
nels. Channels A and C have available packets to send, and channels B and D do not have packets to send. By
driving RxENB[A] low at clock edge 1, the ATM side selects channel A, and packet transfer is started at
clock edge 2. The master samples this data at clock edge 3. At clock edge 4, RxPA[C] shows that channel C also
has a packet to send, and this is reflected to RxPA[A] at clock edge 5. RxPA[B] and RxPA[D] show the direct status
of channels B and D, indicating that they do not have packets to send.
(TxADDR[4:0]) lines.
RxADDR[4:0] (TxADDR[4:0]) during this cycle; RxENB[D:A] (TxENB[D:A]) is deasserted.
made.
R
R
X
R
R
R
X
SOP/C[A]
R
DATA[A]
X
R
R
R
X
R
R
X
X
EOP[A]
ENB[A]
CLK[A]
X
X
X
X
X
ADDR
PA[A]
PA[B]
PA[C]
PA[D]
SZ[A]
Figure 28. RxPA Responses of a Multi-PHY for All Four Channels
HIGH Z
00
HIGH Z
HIGH Z
HIGH Z
1
(PA Response Configured for One Cycle)
1F
00
(continued)
2
HIGH Z
(continued)
P1P2
01
3
P3P4
1F
01
4
HIGH Z
P5P6
02
5
P7P8
1F
02
6
P9P10
HIGH Z
03
155/622/2488 Mbits/s Data Interface
7
P11P12 P13P14 P15P16
1F
03
8
HIGH Z
00
TDAT042G5 SONET/SDH
9
1F
00
10
P17P18
HIGH Z
01
11
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