tdat04622 ETC-unknow, tdat04622 Datasheet - Page 285

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

Data Sheet
May 2001
Agere Systems Inc.
Interface Timing Specifications
Microprocessor Interface Timing
Synchronous Mode (continued)
ADDR[15:0] The address will be available throughout the entire cycle.
DATA[15:0]
R/W (Input)
CS (Input)
DT (Output) Data transfer acknowledge is active-low on the host bus interface. It is initiated in timing cycle T5.
ADS (Input) Address strobe is active-low for one clock cycle, T0. When used with the Power PC* (Motorola
* PowerPC is a registered trademark of International Business Machines Corporation.
† Motorola is a registered trademark of Motorola, Inc.
Table 163. Microprocessor Interface Synchronous Write Cycle Specifications
(See Figure 38 on page 256 for the timing diagram.)
Symbol
t1
t2
t3
t4
t5
t6
t7
ADDR, R/W, DATA (write) Valid to MPCLK
MPCLK to ADDR, R/W, DATA (write) Invalid
CS Valid to MPCLK
ADS Valid to MPCLK
MPCLK to ADS Invalid
MPCLK to DT Valid
MPCLK to DT Invalid
Data will be available during cycles T1 through T5.
The read (H) write (L) signal is always high except during a write cycle.
Chip select is an active-low signal.
DT is 3-stated when CS is high.
MPC860), this is TS (transfer start).
Parameter
(continued)
(continued)
Setup
(Min)
(ns)
155/622/2488 Mbits/s Data Interface
3.5
5.5
—
—
—
—
3
(Min)
Hold
(ns)
TDAT042G5 SONET/SDH
—
—
—
—
5
5
1
Delay
(Max)
(ns)
—
—
—
—
—
—
8
†
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