tdat04622 ETC-unknow, tdat04622 Datasheet - Page 54

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information
Table 3. Pin Descriptions—Line Interface Signals (continued)
Unused LVPECL outputs should not be terminated to minimize power consumption. Unused inputs are internally
disabled whenever core registers 0x0010 and 0x0011 are properly provisioned. The unused inputs can be consid-
ered to be NC (no connect).
26
Pin
M2
M1
M4
M3
H2
P2
P1
P5
P3
N3
N2
N5
N4
K2
K1
K4
K3
J5
L2
L1
L4
L3
J2
J1
J4
J3
TxD[10]N
TxD[11]N
TxD[12]N
TxD[13]N
TxD[14]N
TxD[15]N
TxD[10]P
TxD[11]P
TxD[12]P
TxD[13]P
TxD[14]P
TxD[15]P
TxCKQP
TxCKQN
Symbol
TxD[4]P
TxD[4]N
TxD[5]P
TxD[5]N
TxD[6]P
TxD[6]N
TxD[7]P
TxD[7]N
TxD[8]P
TxD[8]N
TxD[9]P
TxD[9]N
(continued)
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
Type
I/O
O
O
Transmit Line Clock Q. This 155.52 MHz clock is used to clock
out the data in the STS-48/STM-16 mode for forward-directional
timing with the 155 Mbits/s 16-bit parallel-to-2.5 Gbits/s serial
MUX.
For an STS-48/STM-16 contra-clocking interface with the
155 Mbits/s parallel-to-2.5 Gbits/s serial MUX, this clock is not
used. In the contra-clocking mode, a phase-locked version of
TxCKP/N is used to clock out the data. In the contra-clocking
mode, the transmit line clock PLL must be active (see core regis-
ter map 0x0010, bit 5 (PLL_ MODE) on page 112).
This clock is not used in the STS-3/STM-1 or STS-12/STM-4
modes.
Transmit Line Data Outputs (STS-48/STM-16). In STS-48/
STM-16 mode, these pins function as transmit line data outputs
[4:15]. The remaining transmit line data outputs [0:3] are listed
below and are multiplexed for use in the STS-3/STM-1 or STS-12/
STM-4 modes.
The 155.52 Mbits/s 16-bit word parallel bus is converted to a
2.488 Gbits/s serial data stream external to TDAT042G5 by a mul-
tiplexer.
All 32 differential data output pins, TxD[15:0]P/N, are used as the
parallel data output bus in the STS-48/STM-16 mode. These pins
constitute a 155.52 Mbyte/s parallel 16-bit word-aligned to the
TxCKP/N and TxCKQP/N 155.52 MHz transmit line clock.
TxD[15] is the most significant bit and is the first bit transmitted.
TxD[0] is the least significant bit and is the last bit transmitted.
This buffer is internally disabled through proper provisioning when
the input is not active.
Name/Description
Agere Systems Inc.
Data Sheet
May 2001