tdat04622 ETC-unknow, tdat04622 Datasheet - Page 19

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

May 2001
Agere Systems Inc.
UTOPIA (UT)
UT11. Clearing UT Interrupt Register
When a UT interrupt event occurs and COW mode is enabled, writing to UT interrupt register 0x0201 does not
clear the register (this register is read-only). The interrupt is cleared by writing to the UT delta and event registers
(addresses 0x0202—0x0205).
Workaround
This is informational only. No workaround is available for this condition.
Corrective Action
No corrective action is required for this condition.
UT12. Incorrect Implementation of POS Multi-PHY Mode
Because the TDAT042G5 lacks a selected PA signal (SPA), the status of a channel that is transmitting data in POS
MPHY mode is not known during polling. Therefore, the PA signal cannot be used as a data valid signal. If the
channel transmitting data runs dry, the master side may receive invalid data.
Workaround
Use direct status polling mode only and ensure that the address of channel A is applied to the address bus at all
times, except during the clock cycle when another channel is being selected.
Corrective Action
No corrective action is required for this condition.
UT13. Invalid Extra Cycle Between EOP and SOP in CRC-16/32 Mode
When using the device in CRC-16 or CRC-32 mode, there is always an extra cycle between the end of packet
(EOP) of the previous packet and the start of packet (SOP) of the following packet.
Workaround
This is informational only. No workaround is available for this condition.
Corrective Action
This is condition will be addressed in the future version of the device.
(continued)
for Version 1 and 1A of the Device
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