tdat04622 ETC-unknow, tdat04622 Datasheet - Page 116

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface
Functional Description
UTOPIA (UT) Interface Block
UT Clocking
TDAT042G5 is compliant with the U2 standard
slave device. The U2 standard and proposed U3 specifications define the slave device transmit path (egress) clock
as an input clock. For the U2 case, the slave transmit path clock is generated by the UT master device. For the cur-
rent version of the U3 specification
same external clock source
receive path (ingress) clock as an input clock. In the U2 case, the slave device receive path (ingress) clock is gen-
erated by the UT master device. In the U3 case, the receive clock for both the master and slave devices is gener-
ated by same external clock source. Previous proposed versions of the U3 specification provided for the case
where the receive path clock could be generated by the slave device. TDAT042G5 can be provisioned in the con-
figuration where it sources the receive path (ingress) clock.
The timing specification for the UT clock is given in the UTOPIA Interface Timing section, pages 268—270.
UT Transmit Path (Egress) Clock
In all UTOPIA modes, the transmit path clock must be provided to TxCLK[D:A] pins as described in Table 5, page
page 31.
UT Receive Path (Ingress) Clock
The receive path clock RxCLK[D:A] pins can be provisioned to be either clock inputs or outputs as described in
Table 5, page 38. Provisioning as either an input or output is done on a per-channel basis through registers
0x020F, 0x0213, 0x0217, and 0x021B (CLOCK_MODE_Rx). In the U2 mode, RxCLK is always provisioned to be
an input. To meet the latest proposed U3 specification, RxCLK is provisioned as an input. To meet special UT
requirements, RxCLK may be provisioned to be a clock output signal. When provisioned as a clock output, the
RxCLK[D:A] is derived from the corresponding TxCLK[D:A] input.
For RxCLK rates greater than 52 MHz, RxCLK must be provisioned to be an output.
1. UTOPIA Level 2, Version 1.0, AF-PHY-0039.000, June 1995.
2. UTOPIA Level 3 Baseline Text, UL3-01.04, February 1999.
3. UTOPIA Level 3 Living List, UL3-01.04, February 1999.
4. UTOPIA Level 3 Living List, LTD-PHY-UL3-01.05, April 1999.
5. UTOPIA Level 3, STR-PHY-UL3-01.00, July 1999.
6.UTOPIA Level 3, AF-PHY-136.00, October 1999.
7.Previous proposed versions of the U3 specification were similar to the U2 standard where the slave device transmit clock was gen erated by
88
the UT master device.
7
. The U2 standard and current U3 proposed specification
(continued)
6
(continued)
, the transmit path clock for both slave and master devices is generated by the
1
and several versions of the proposed U3 specification
6
define the slave device
Agere Systems Inc.
Data Sheet
2—6
May 2001
as a UT