tdat04622 ETC-unknow, tdat04622 Datasheet - Page 239

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

Data Sheet
May 2001
Agere Systems Inc.
Register Descriptions
DE Registers
This section gives a brief description of each register bit and its functionality. All algorithms are described in the
main text of the document. The abbreviations after each register indicate if the register is read only (RO), read/write
(R/W), write only (WO), or clear-on-read or clear-on-write (COR/W).
0x indicates a hexadecimal value in the Reset Default column. Otherwise, the entry is binary. This is true for every
register table in the document.
Table 111. Register 0x1000: DE Macrocell Version Number (RO)
Reset default of register = 0x0001.
Table 112. Register 0x1001, 0x1002: DE Interrupts (0x1001 is RO, 0x1002 is RO and COR/W)
Reset default of registers = 0x0000.
Note: Register 0x1001 is cleared by accessing the source register of the interrupt. The source register must be
Address
Address
(Hex)
1001
(Hex)
1000
read and cleared to clear these registers.
15—5
Bit #
3—0
15—0
Bit #
4
DEINT_SDLMS
DEINTCH[3:0]
DE_VERSION
Name
Name
—
(continued)
Reserved. These bits must be written to their reset default
value (00000000000).
SDL Message Sent Interrupt.
Note: This bit indicates that the SDL frame inserter is
Channel Interrupt. Active-high interrupt bit on a per-
channel basis. These bits are the ORing of all interrupt bits
associated with the error counters described in registers
0x1100—0x111F (pages 238—page 143). The error counter
can be inhibited from contributing to the interrupt by setting the
appropriate mask bit in register
DEDINTM[0—3] (addresses 0x1180, 0x1182, 0x1184, 0x1186
on page 243).
The following interrupts will generate a DE interrupt:
Bit 0 corresponds to channel 0 interrupt.
Bit 1 corresponds to channel 1 interrupt.
Bit 2 corresponds to channel 2 interrupt.
Bit 3 corresponds to channel 3 interrupt.
Note: This bit indicates that the channel is experiencing an
Macrocell Version Number. The version of the macrocell will
increment each time a change occurs to the macrocell
functionality.
experiencing an interrupt. This bit will not clear on a
read or a write of this register, but will clear when the
SDL SDLMSI register (0x1606, bit 0) is read.
These interrupts will generate a DE interrupt.
interrupt. This bit will not clear on a read or a write of
this register, but will clear when the counter interrupt
register DEDINTM[0—3] (addresses 0x1181, 0x1183,
0x1185, 0x1187 on page 244) is read or written.
Function
Function
155/622/2488 Mbits/s Data Interface
TDAT042G5 SONET/SDH
Default
Reset
Default
0x0001
0000
0000
Reset
000
0x0
0
211