tdat04622 ETC-unknow, tdat04622 Datasheet - Page 240

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface
Register Descriptions
DE Registers
Table 112. Register 0x1001, 0x1002: DE Interrupts (0x1001 is RO, 0x1002 is RO and COR/W) (continued)
Reset default of registers = 0x0000.
Notes: Register 0x1002 must be used only in the COR mode, where core register 0x0010, bit 6 = 1.
212
Address
(Hex)
1002
Bits 15—12, SDL Rx frame state interrupt (DEINT_SDLRxFS), are read only. Bits 15—12 are cleared by
reading and clearing the corresponding interrupt source registers, 0x14E0—0x14E3.
15—12
11—8
Bit #
(continued)
DEINT_ATMRxAC
DEINT_SDLRxFS
(continued)
Name
SDL Rx Frame State Interrupt. This interrupt
is generated when the SDL frame state is
transitioned from sync to hunt. This bit is
cleared when read only.
The following interrupts will generate a DE
interrupt:
Bit 12 corresponds to channel 0 interrupt.
Bit 13 corresponds to channel 1 interrupt.
Bit 14 corresponds to channel 2 interrupt.
Bit 15 corresponds to channel 3 interrupt.
ATM Rx All-Cool Interrupt. This interrupt is
generated when the payload of received null/
idle cells is correctly incrementing. This bit may
clear when read or written. This interrupt is
used in conjunction with the optional
incrementing payload sequence mode for
debug purposes and is used in conjunction with
DE register 0x12F0.
Bit 8 corresponds to channel 0 interrupt.
Bit 9 corresponds to channel 1 interrupt.
Bit 10 corresponds to channel 2 interrupt.
Bit 11 corresponds to channel 3 interrupt.
Note: This signal does not generate a DE
interrupt under any circumstances.
Function
Agere Systems Inc.
Data Sheet
May 2001
Default
Reset
0x0
0x0