tdat04622 ETC-unknow, tdat04622 Datasheet - Page 273

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

Data Sheet
May 2001
Agere Systems Inc.
Register Descriptions
DE Registers
Table 147. Registers 0x1200—0x1213, 0x12F0: ATM Transmit Registers (R/W) (continued)
Reset default of registers 0x1200—0x1203, 0x12F0 = 0x0000.
Reset default of registers 0x1210—0x1213 = 0x0001.
Address
(Hex)
12F0
15—8
Bit #
5—4
3—2
1—0
(continued)
—
7
6
ATM_HEADER_ERROR ATM Tx Debug Control. Used for debug
(continued)
Name
—
—
—
—
—
—
purposes to inject errors, and to increment the
payload sequence for NULL cells.
Reserved. These bits must be written to their
reset default value (0x00).
Incrementing Null (Idle) Cell Payload
Sequence. This bit governs whether 0x6A is
used for the payload of NULL cells, or whether an
incrementing 8-bit count is used (0x00 → 0xFF).
A value of 1 selects the incrementing sequence.
This is used with DE register 0x1002 bits [11:8].
Error Strobe. Writing a value of 1 to this register
initiates the injection of a single or double shot
error injection, assuming one of these two modes
is selected.
Error Injection Mode. These bits control the
mode of operation of the error injection.
00 = continuous injection
01 = single shot (isolated cell)
10, 11 = double shot (i.e., two back-to-back cells)
Error Type. These bits control the injection of a
walking error pattern into the headers of all
outgoing cells.
00 = no errors
01 = single bit errors
10, 11 = double bit errors
Error Channel ID. The logical channel in which
to inject the header errors.
Function
155/622/2488 Mbits/s Data Interface
TDAT042G5 SONET/SDH
Default
0x0000
Reset
0x00
00
00
00
0
0
245