tdat04622 ETC-unknow, tdat04622 Datasheet - Page 306

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface
DS98-193SONT-4 Replaces DS98-193SONT-3 to Incorporate the Following
Updates
27.Page 71, ATM Cell Processor section under Data Engine (DE) Block, expanded.
28.Page 75, PPP Header Detach section, added footnote and updated Figure 16, Uncompressed and Com-
29.Page 77 and page 94, HDLC Inserter in the Data Engine (DE) Block section and FIFO in the UT Transmit Input
30.Page 82, Data Engine (DE) Block, Over-Fiber Modes section, clarified description.
31.Page 83, Transparent Payload Mode section, updated.
32.Page 85, Table 24, UTOPIA Traffic Types, updated.
33.Page 86, UTOPIA ATM Cell Processing section, added.
34.Page 88, added UT Clocking, UT Transmit Path (Egress) Clock, UT Receive Path (Ingress) Clock sections;
35.Page 90, Two-Cycle Delay Mode section, provided reference for RxPA[D:A] definition.
36.Page 91 and page 92, updated Figure 23, Receive-Side Interface Handshaking in Point-to-Point, Single Cycle
37.Page 93, Transmit Cell/Packet Available (TxPA) section, expanded definition.
38.Page 94, Table 29, Egress High Watermark Thresholds, added.
39.Page 95, Figure 25, Transmit-Side Interface Handshaking in Point-to-Point, Single Cycle Mode, updated.
40.Page 96, Multi-PHY Support section, clarified the concept of point-to-point vs. polled mode configuration.
41.Page 100, JTAG (Boundary-Scan) Test Block section, added second paragraph.
42.Page 100, Reset of JTAG Logic section, added.
43.Page 100, Line Interface section added to document (including Table 30).
44.Page 102, General-Purpose I/O Bus (GPIO) section, expanded.
45.Page 105, Performance Monitor Reset (PMRST) section, expanded.
46.Page 106, Far-End Loopback, Terminal Loopback, Facility Loopback, expanded sections.
47.Page 108—page 110, Figur e34, Single ATM UTOPIA 3; Figur e36, Single POS UTOPIA 3, updated.
48.Page 112 and p age152, GPIO Output Configuration register (addresses 0x0014 and 0x0015), updated in Reg-
49.Pages 124—125, 191, TZ0DINS[A—D][2—12][7:0] registers (addresses 0x05AA—0x05C1), updated in the
50.Page 119, Register Maps section, corrected subtitle in OHP map from Signal Degrade Set/Clear Control Regis-
51.Page 120, Register Maps section, corrected subtitle in OHP map from Signal Fail Set/Clear Control Registers to
52.Pages 119—121, 136, 185—186, 198, Register Maps and Register Descriptions sections, differentiated bit-
53.Pages 134—135, 199, changed bits [15:9] from Reserved to RPOHMONSEL[A—D][3:0] and RCONC_ALLOR
278
pressed PPP Packets.
Path (Egress) section, corrected description of 0x7D20.
removed Clocks section on page 91.
Mode; added Figure 24, Receive-Side Interface Handshaking in Point-to-Point, Two-Cycle Mode.
ister Maps and Register Descriptions sections.
Register Maps and Register Descriptions sections.
ters to Signal Degrade BER Algorithm Parameters.
Signal Fail BER Algorithm Parameters.
names in OHP sections from bitnames in PT sections for signal degrade and signal fail BER algorithm parame-
ters.
FIRST[A—D] in the Register Maps and Register Descriptions sections.
(continued)
Agere Systems Inc.
Data Sheet
May 2001