tdat04622 ETC-unknow, tdat04622 Datasheet - Page 122

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface
Functional Description
UTOPIA (UT) Interface Block
UT Transmit Input Path (Egress) (continued)
FIFO. The UTOPIA Tx FIFO is used to create an elastic store that can buffer bursts of data received via the UTO-
PIA Tx, faster than can be transmitted out of the path. After the FIFO exceeds a programmable watermark, it indi-
cates to the UTOPIA Tx master to stop sending data. The master can choose to ignore this request causing the
risk of an overflow. The FIFO block buffers 256 bytes of cell/packet data. The FIFO accommodates four ATM cells
or 256 bytes of packet data. The FIFO is required to manage the asynchronous nature of the UTOPIA interface.
Optionally, in the case of FIFO underflow, a 0x7D207D207D20 . . . will be inserted by the data engine into the mid-
dle of the packet if dry mode is provisioned and the default dry escape sequence is used (0x7D20, where the last
two bytes (the 20 bytes of the default value of 0x7D20) are provisionable). This will be removed at the far end by
the device (provided the link is comprised of two devices and both sides of the link support dry mode).
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FIFO Watermark Threshold. When carrying ATM cell traffic, this threshold, while measured in words, should be
set at least one cell’s length from end of FIFO. The UTOPIA Tx interface, by definition, must be able to accept an
entire ATM cell after the current ATM cell, unless TxPA is deasserted at least four clock cycles before the end of
the current cell transfer.
When carrying packet traffic, however, the threshold can be set higher, as the UTOPIA Tx interface only needs
to accept a limited number of words after deasserting TxPA. The number of words is a programmable value for
the sender, and should be assumed to be at least 2 words for the purposes of setting the threshold.
FIFO high watermark threshold, EGRESS_WATERMARK_HIGH_[A—D][6:0] (addresses 0x0212, 0x0216,
0x021A, 0x021E), should be set as follows.
Table 29. Egress High Watermark Thresholds
Note: The high watermark threshold should be set less than the values in the above table assuming there is no
UTOPIA Mode
16-bit, U2+
32-bit, U3+
8-bit, U3+
delay between TxPA deassertion and TxENB deassertion. Then the threshold values may be changed to
optimize UT egress performance and to avoid FIFO overflow.
Maximum Threshold Value
(continued)
(continued)
0x3D
0x3B
0x37
Agere Systems Inc.
Data Sheet
May 2001