tdat04622 ETC-unknow, tdat04622 Datasheet - Page 202

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface
Register Descriptions
OHP Registers
Table 79. Registers 0x0422—0x042D: Receive Control (R/W) (continued)
Reset default of registers = 0x0000.
174
0422, 0424,
0426, 0428
Address
(Hex)
Bit #
9
8
7
6
5
4
3
2
1
0
(continued)
S1MON8_OR_4CTL[A—D] S1 Byte or Nibble. When set to logic 1, the S1
K1K2_2_OR_1[A—D]
B2BITBLKCNT[A—D]
B1BITBLKCNT[A—D]
ROH_BYPASS[A—D]
LOS_AISINH[A—D]
CNTDB1SEL[A—D]
SDB1B2SEL[A—D]
SFB1B2SEL[A—D]
DSCRINH[A—D]
(continued)
Name
Loss-of-Signal AIS Inhibit. When set to logic
1, the line AIS insertion will be inhibited in case
of loss-of-signal.
Signal Fail B1/B2 Error Count Select. When
set to logic 0, the B1 errors will be used by the
signal fail error rate algorithm; otherwise, B2
errors are used.
Signal Degrade B1/B2 Error Count Select.
When set to logic 0, the B1 errors will be used
by the signal degrade error rate algorithm; oth-
erwise, B2 errors are used.
Reset CNTD Counters on B1 Error. Active-
high control bits to reset continuous N time
detect counters upon received B1 errors. Only
CNTDB1SEL[0] is valid for STS-48/STM-16.
byte will be monitored as two nibbles. Other-
wise, it is treated as a byte. Only
S1MON8or4CTL[A] is valid for STS-48/STM-
16.
K1 and K2 Treated as 2 Registers or 1. When
a bit is set to 1, the K1 and K2 bytes will be
treated as one 16-bit register. Otherwise, they
will be treated as two registers of size 13
(K1[7:0] and K2[7:3]) and 3 (K2[2:0]).
K1K2_2_OR_1[A] is valid for STS-48/STM-16.
B2 Error Count in Bit or Block. When set to 0,
B2 check logic will count bit errors; otherwise, it
counts block errors. Only B2BITBLKCNT[A] is
valid for STS-48/STM-16.
Descramble Inhibit Control. When a bit is set
to 1, the descrambler for that is disabled. In
STS-48/STM-16 mode, all 4 bits need to be set
to same value.
B1 Error Count in Bit or Block. When set to 0,
B1 check logic will count bit errors; otherwise, it
counts block errors. Only B1BITBLKCNT[A] is
valid for STS-48/STM-16.
Receive Overhead Bypass. Control bit, when
set to 1, causes the received data to pass
through the block retimed. In STS-48/STM-16
mode, all 4 bits need to be set to same value.
Function
Agere Systems Inc.
Data Sheet
May 2001
Default
Reset
0
0
0
0
0
0
0
0
0
0