tdat04622 ETC-unknow, tdat04622 Datasheet - Page 74

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface
Overview
Figure 3 shows the interface diagram of the IC.
The receive path terminates and processes section, line, and path overhead. It performs framing (A1, A2),
descrambling, detects alarm conditions, and monitors section, line, and path BIP-Ns (B1, B2, B3), accumulating
error counts for each level for performance monitoring purposes. Line and path remote error indications (M1, G1)
are also accumulated. The payload pointers (H1, H2) are interpreted, and the synchronous payload envelope
(SPE) is extracted.
The transmit path inserts section, line, and path overhead. It inserts the framing pattern (A1, A2), performs scram-
bling, inserts AIS (optionally), and calculates and inserts section, line, and path BIP-8s (B1, B2, B3). Line and path
remote failure indications (M1, G1) are inserted based on received BIP-8 errors. The payload pointers (H1, H2) are
generated, and the SPE is inserted.
When used to implement an ATM UNI, ATM cells are written into an internal 4-cell FIFO buffer using a generic
8-/16-/32-bit wide UTOPIA 2/3 compliant interface. Idle/unassigned cells are automatically inserted when the inter-
nal FIFO is empty. The device provides generation of the header check sequence and optionally scrambles the
ATM payload.
46
STS-48/STM-16
STS-48/STM-16
STS-12/STM-4
STS-12/STM-4
STS-3/STM-1
STS-3/STM-1
(continued)
INTERFACE
TOH
PROCESSOR
PROCESSOR
OVERHEAD
OVERHEAD
INTERFACE
OVERHEAD
TRANSMIT
RECEIVE
Figure 3. Interface Block Diagram
INTERPRETER
INTERFACE
POINTER
MAPPER
MPU
SPE
FRAME INSERTION
ENCAPSULATION
DECAPSULATION
UNSCRAMBLING
ATM/HDLC/SDL
ATM/HDLC/SDL
SCRAMBLING
INTERFACE
FRAME
JTAG
UTOPIA
UTOPIA
Tx
Rx
Agere Systems Inc.
ENHANCED
UTOPIA
INTERFACE
Data Sheet
May 2001
5-6746(F)r.11