tdat04622 ETC-unknow, tdat04622 Datasheet - Page 63

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

Data Sheet
May 2001
Agere Systems Inc.
Pin Information
Table 5
AM13
AM12
AM11
AM10
AR12
AP12
AN12
AR11
AP11
AN11
AR10
AP10
AN10
AR22
AL13
AL12
AL10
AL21
AJ33
AJ32
AR9
AP9
U31
T34
Pin
.
Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)
RxDATA[D][15]
RxDATA[D][14]
RxDATA[D][13]
RxDATA[D][12]
RxDATA[D][11]
RxDATA[D][10]
RxDATA[D][9]
RxDATA[D][8]
RxDATA[D][7]
RxDATA[D][6]
RxDATA[D][5]
RxDATA[D][4]
RxDATA[D][3]
RxDATA[D][2]
RxDATA[D][1]
RxDATA[D][0]
RxSOP/C[D]
RxSOP/C[C]
RxSOP/C[B]
RxSOP/C[A]
RxPRTY[D]
RxPRTY[C]
RxPRTY[B]
RxPRTY[A]
Symbol
(continued)
Type
3.3 V
3.3 V
3.3 V
I/O
O
O
O
Receive Data Channel D. Used to transport data out of the
UTOPIA PHY Rx block. RxDATA[D][15:0] is only valid when
RxENB[D] is asserted, and is updated on the rising edge of
RxCLK[D]. Note that RxDATA[D][15:0] is used in various UTO-
PIA modes. In U2 or U2+, all 16 bits are valid. In U3+ (8-bit
mode), only bits 15 to 8 are valid.
In U3 or U3+ (32-bit mode), channel D port must be provisioned
to idle mode.
Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB).
Receive Parity. This signal indicates the parity on the
RxDATA[D:A][15:0]. Odd or even parity may be provisioned
through a software register. RxPRTY[D:A] is considered valid
only when RxENB[D:A] is asserted, and is updated on the rising
edge of RxCLK[D:A].
In U3 or U3+ (32-bit mode), the RxPRTY[A] parity pin of port A
indicates the parity for the entire 32-bit data output.
Receive Start of Packet/Cell. In ATM mode, RxSOP/C[D:A]
signal marks the start of a cell on the RxDATA[D:A][15:0] bus.
When RxSOP/C[D:A] is high on the clock cycle following the
latching of an active RxENB[D:A] signal, the first word of the cell
structure is present on the RxDATA[D:A][15:0] bus.
In packet modes, the RxSOP/C[D:A] signal marks the start of a
packet on the RxDATA[D:A][15:0] bus. When RxSOP/C[D:A] is
high, the first word of the packet is present on the
RxDATA[D:A][15:0] bus.
RxSOP/C[D:A] is considered valid only when RxENB[D:A] is
asserted, and is updated on the rising edge of RxCLK[D:A].
In U3 or U3+ (32-bit mode), only the RxSOP/C[A] pin of port A is
used to indicate a start of packet/cell for the 32-bit data output.
Name/Description
155/622/2488 Mbits/s Data Interface
TDAT042G5 SONET/SDH
35