tdat04622 ETC-unknow, tdat04622 Datasheet - Page 61

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tdat04622

Manufacturer Part Number
tdat04622
Description
Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
Manufacturer
ETC-unknow
Datasheet

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Data Sheet
May 2001
Agere Systems Inc.
Pin Information
Table 5
AM18
AM30
AN17
AA31
AA35
AP20
AL29
AL32
AL33
W32
W31
H32
N31
N32
N33
N34
R31
R32
R33
R34
R35
P31
P32
P33
P34
P35
T32
T33
J31
Pin
.
Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)
RxDATA[A][15]
RxDATA[A][14]
RxDATA[A][13]
RxDATA[A][12]
RxDATA[A][11]
RxDATA[A][10]
RxDATA[A][9]
RxDATA[A][8]
RxDATA[A][7]
RxDATA[A][6]
RxDATA[A][5]
RxDATA[A][4]
RxDATA[A][3]
RxDATA[A][2]
RxDATA[A][1]
RxDATA[A][0]
RxADDR[4]
RxADDR[3]
RxADDR[2]
RxADDR[1]
RxADDR[0]
TxEOP[D]
TxEOP[C]
TxEOP[B]
TxEOP[A]
TxERR[D]
TxERR[C]
TxERR[B]
TxERR[A]
Symbol
(continued)
(5 V tolerant)
(5 V tolerant)
(5 V tolerant)
3.3 V
3.3 V
3.3 V
3.3 V
Type
I/O
O
I
I
I
Transmit End of Packet. These pins are used only in U2+
and U3+ (packet) modes. This signal indicates that the last
word of a packet is on the TxDATA[D:A][15:0] bus.
TxEOP[D:A] is valid only when TxENB[D:A] is asserted, and
is sampled on the rising edge of TxCLK[D:A].
In U3+ (32-bit mode), only the TxEOP[A] input pin of port A
is used to indicate the end of the incoming packet.
Transmit Error. These pins are used only in U2+ and U3+
(packet) modes. TxERR[D:A] is only used in packet modes,
and indicates that the current packet is to be aborted and
discarded, if possible. TxERR[D:A] is only valid when
TxEOP[D:A] and TxENB[D:A] are asserted, and is sampled
on the rising edge of TxCLK[D:A].
In U3+ (32-bit mode), the TxERR[A] and the TxERR[B] input
pin of port A is used to indicate an error on the incoming
packet.
Receive Address. Receive address is driven to the MPHY
to poll and select the appropriate MPHY channel.
Note: The address for each channel is configured by the
Receive Data Channel A. Used to transport data out of the
UTOPIA PHY Rx block. RxDATA[A][15:0] is only valid when
RxENB[A] is asserted, and is updated on the rising edge of
RxCLK[A]. Note that RxDATA[A][15:0] is used in various
UTOPIA modes. In U2 or U2+, all 16 bits are valid. In U3 or
U3+ (8-bit mode), only bits 15 to 8 are valid.
In U3 or U3+ (32-bit mode), RxDATA[A][15:0] forms the most
significant 16 bits of the combined data bus (bits 31 to 16),
and RxDATA[B][15:0] forms the least significant 16 bits of the
combined data bus (bits 15 to 0).
Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB).
microprocessor.
Name/Description
155/622/2488 Mbits/s Data Interface
TDAT042G5 SONET/SDH
33

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