tdat04622 ETC-unknow, tdat04622 Datasheet - Page 128

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface
Functional Description
JTAG (Boundary-Scan) Test Block
The JTAG test block provides an IEEE 1149.1 JTAG controller interface for memory BIST, boundary scan, and
32-bit ID register instructions. Details about JTAG (boundary-scan) functionality and interface timing specifications
can be found in MN98-060ASIC-02, HL250C 3.3 Volt 0.25 µ m CMOS Standard-Cell Library Manual, page 8-1
through page 8-31.
The instruction register length is 3 bits.
Reset of JTAG Logic
There are two events that will reset the JTAG logic:
I
I
TRST can be held high during normal device operation only if TRST is pulled low upon powerup.
Line Interface
LVPECL I/O Termination and Load Specifications
The LVPECL buffers are compatible with the temperature independent ECL 100K levels, but the output levels that
are guaranteed are relaxed 30 mV from the actual 100K levels allowing for noise and variations in the power sup-
ply and process.
All LVPECL output buffers require a terminating resistor. These terminating resistors, which must also be con-
nected to both LVPECLREFHI and LVPECLREFLO, go to a common terminating voltage. All of the terminating
resistors used with a chip must be identical precision (1%) resistors. The value of these terminating resistors is
usually chosen to match the characteristic impedance of the board. To save on power, a terminating voltage equal
to V
these bufers is 50 Ω. This is also the standard termination used in most ECL systems. Larger values of resistance
will save power, but will also slow down the high-to-low transition of the output, since it is RC limited.
if no V
such that the current through it does not exceed the current through a 50 Ω resistor to V
high state). This large resistor will most likely be a poor match to the board impedance. The match can be
improved by the user of a Thevenin equivalent resistor pair. Such a Thevenin equivalent resistor will burn much
more system power (but not on-chip power) than would a single resistor, but it does allow for impedance matching
in the absence of aV
Experienced ECL designers sometimes use the (bipolar) ECL output buffers in a tied-OR configuration. Unfortu-
nately, this cannot be done with these LVPECL buffers.
Table 30. Nominal dc Power for Suggested Terminations
Note: The value is the average of the high and low states in LVPECL output buffer and external terminating resis-
1.
2.
100
Pulse or pull the TRST pin signal low with no TCK pin signal present. TRST is pulled high on-chip.
The TMS pin signal is driven high for five cycles of TCK. TMS is pulled high on-chip.
Terminating Resistor and Voltage
125 Ω to V
DDD
DDD
tors, for a single-ended output. The values double for double-ended outputs.
Standard ECL termination (parallel).
Thevenin equivalent or 50 Ω to V
– 2 V is available in most ECL systems. The minimum value of the terminating resistor that can be used on
50 Ω to V
– 2 V supply is available, a larger value resistor may be connected directly to GND. It should be chosen
DDD
and 83 Ω to GND
DDD
DDD
– 2 V
– 2 V supply. Termination resistor options are shown in Table 30.
1
(continued)
DDD
2
– 2 V.
Output Transistor (on-chip)
Power (mW)
15
15
Terminating Resistor (off-chip)
Power (mW)
DDD
13
52
– 2 V (21 mA in the
Agere Systems Inc.
Data Sheet
May 2001