tdat04622 ETC-unknow, tdat04622 Datasheet - Page 70

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information
Table 8. Pin Descriptions—JTAG Interface Signals
* I
Note: JTAG interface signals are used for test operations that are carried out using the IEEE P1149.1 test access port. IEEE is a registered
42
u
Pin
G5
G2
G3
F2
F4
= I
trademark of The Institute of Electrical and Electronics Engineers, Inc.
d
= 50 kΩ, where I
Symbol
TRST
TMS
TDO
TCK
TDI
u
= internal pull-up resistance and I
(continued)
(5 V tolerant)
(5 V tolerant)
(5 V tolerant)
(5 V tolerant)
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Type
I/O*
O
I
I
I
I
u
u
u
u
JTAG Test Clock. This 10 MHz signal provides timing for test
operations.
JTAG Test Mode Select. Controls test operations. TMS is sam-
pled on the rising edge of TCK.
JTAG Test Data In. Provides a 10 Mbits/s test data input signal.
TDI is sampled on the rising edge of TCK.
JTAG Test Data Out. This 10 Mbits/s data output signal is
updated on the falling edge of TCK. The TDO output is 3-stated
except when scanning out test data.
JTAG Test Reset (Active-Low). This signal provides an asyn-
chronous reset for the TAP. Under normal device operations,
TRST should be pulled low. TRST is a Schmitt-triggered input.
d
= internal pull-down resistance.
Name/Description
Agere Systems Inc.
Data Sheet
May 2001