tdat04622 ETC-unknow, tdat04622 Datasheet - Page 125

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

Data Sheet
May 2001
Agere Systems Inc.
Functional Description
UTOPIA (UT) Interface Block
Multi-PHY Support (continued)
In 8-bit or 16-bit multi-PHY mode, only the data bus and the control signals (except the RxPA or TxPA signal) of
channel A are active for the polled group. RxPA[A] indicates the packet/cell availability of the selected or polled
channel. Similarly, TxPA[A] indicates transmit FIFO availability for a selected or polled channel. The remaining
RxPA/TxPA signals for the polled channels are activated and indicate instantaneous or direct status of the particu-
lar channel. In 32-bit multi-PHY mode, the data bus and size control signals of channel B are also active.
TDAT042G5 does not provide a selected packet available (SPA) signal to monitor the status of the current channel
sending/receiving data to or from the master. To prevent the FIFOs from running dry or overflowing in the middle of
a packet transfer, the user must design the UT TDAT042G5 slave-to-master interface with direct status mode
rather than address polling. The direct status of each channel is provided on the associated SPA pin for that chan-
nel. In this mode, the user must guarantee that when channels are switched to receive data from a channel other
than channel A, they immediately reapply the address of channel A to the address bus after the new channel is
selected. The user then gets the direct status SPA signal from channel A. Channels B, C, and D are always directly
sent out of the TDAT042G5. In either receive or transmit, when direct status is used in addition to the direct status
pin for a given interface, its corresponding interface clock pin must be driven by the clock of the A interface.
During the cycle when the selected channel is being changed, the address of the new channel is placed on the
address bus. The user must ignore the RxPA response of the initial channel during the expected response time
(one or two cycles later, depending on the PA response bit when the address of the newly selected channel was
applied).
Figure 27 illustrates the transmit interface timing for the case when the direct status of packet available of channels
A, B, C, and D is present. In this example, channels A and C indicate they can receive data. When the SPA signal
for C is observed, a channel switch is performed by the master by deasserting TxENB and placing the address of
channel C on the address bus. On the following cycle, data is placed on the bus along with the start of packet. In
this example, the TxPA response is configured for two cycles so that the PA response of address 02 results in the
PA of channel C to appear on channel A’s output two clock cycles later. Subsequent data sent to the slave will go
to channel C (i.e., data values I, J, etc.).
When the RxPA signals are used for multi-PHY (MPHY) direct status, the corresponding RxCLK[B, C, and/or D]
must be provided. They may be provided via an external UT master, or they may be sourced from the correspond-
ing TxCLK[D:A] pin by using the UT clock source mode (see UT Clocking, page 88).
(continued)
(continued)
155/622/2488 Mbits/s Data Interface
TDAT042G5 SONET/SDH
97